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Conception d'un circuit intégré pour la visualisation graphique

Abstract : Increased use of graphic display units is prevented by the high cost of existing devices. Lowering their costs suggests the use of TV sets. Display electronics for such a raster-scan unit will include a screen memory containing the state of all displayable points, that is up to 256 K bits for a 512 x 512 B&W display and more for colour applications. Technological advances in NMOS memories make such memory sizes cheaper and cheaper. The control part ensuring screen refresh, memory management, vector and character generation and computer coupling remains very complex. Design of microprocessor-oriented Large-Scale-Integrated circuit including all these functions is the topic of this work.
The chip permits a decent writing speed of one point per 1,3 microseconde and a great versatility, as well for screen memory organization as for microprocessor interface. Display resolution from 64 x 64 to 512 x 512 points are possible, with any number of colours or gray levels. Microprocessor interface is standard: an eight bits bidirectional data bus, a four bits address bus, read-write signals and an interrupt request.
In order to simplify the topological layout of such a circuit (equivalent complexity of 2000 gates) of a non-repetitive structure, logical and geometrical design of elementary building blocks is defined. Functional structure of each part of the circuit is then studied, followed by its topological layout using as much as possible the available building blocks.
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Contributor : Philippe Matherat <>
Submitted on : Monday, October 8, 2007 - 11:15:42 AM
Last modification on : Wednesday, December 9, 2020 - 3:12:27 PM
Long-term archiving on: : Sunday, April 11, 2010 - 10:24:20 PM


  • HAL Id : tel-00177458, version 1


Philippe Matherat. Conception d'un circuit intégré pour la visualisation graphique. Micro et nanotechnologies/Microélectronique. Université Pierre et Marie Curie - Paris VI, 1978. Français. ⟨tel-00177458⟩



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