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Conception et validation d'une « puce patch-clamp » en silicium pour paralléliser et automatiser les mesures électriques sur cellules individualisées.

Abstract : Planar patch-clamp, a method to measure ionic currents by using on-planar substrate structured microholes, allows parallelizing measurements as needed by pharmaceutical companies. First, we have made a device allowing us to test our silicon chip and to demonstrate its ability to record ionic currents. Then, we have made improvements to the chip performances and sensitivity by optimizing the interaction of living cells with geometrical and physico-chemical parameters of the chip and by decreasing the chip capacitance. Thanks to this method, we have designed a chip leading to more than 80 % of usable seals and electrophysiological experiments presented in this study reveal the robustness, the reliability and the sensitivity of the device.
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https://tel.archives-ouvertes.fr/tel-00174805
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Submitted on : Tuesday, September 25, 2007 - 12:56:15 PM
Last modification on : Wednesday, November 4, 2020 - 3:17:55 PM
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  • HAL Id : tel-00174805, version 1

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Thomas Sordel. Conception et validation d'une « puce patch-clamp » en silicium pour paralléliser et automatiser les mesures électriques sur cellules individualisées.. Autre [q-bio.OT]. Institut National Polytechnique de Grenoble - INPG, 2006. Français. ⟨tel-00174805⟩

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