Skip to Main content Skip to Navigation

Le transistor MOS de puissance à tranchées : modélisation et limites de performances

Abstract : This thesis deals with the modelling and evaluation of performance of a new power device, referred to as the trench MOS transistor. More precisely, the development, as from the seventies onward, of the low voltage power MOS structures is first presented up to the advent of the trench MOSFET whose main properties are listed. Then, a study of mechanisms involved in the different zones of the device - i.e., static analysis under ON-state and OFF-state, dynamic analysis - is carried out. Based on this study, a model of this transistor is established for the electric circuit simulation software SPICE. Parameter acquisition procedures for this model are detailed. The model thus obtained is then validated on two families of various industrial power MOSFET's. Finally, the static and dynamice performance limits of VDMOS and trench MOS structures are surveyed and compared. It is primarly shown that in the field of low voltages, the trench MOSFET exhibits higher performance standards than the VDMOS structure in terms of specific on-resistance and cell integration density. Analytical studies along with the 2D simulations of these types of devices equally show that this superiority is bound to increase in the yeards to come.
Complete list of metadata
Contributor : Emilie Marchand <>
Submitted on : Thursday, July 26, 2007 - 4:35:48 PM
Last modification on : Thursday, June 10, 2021 - 3:05:23 AM
Long-term archiving on: : Monday, June 27, 2011 - 3:20:21 PM


  • HAL Id : tel-00165581, version 1


Frédéric Morancho. Le transistor MOS de puissance à tranchées : modélisation et limites de performances. Micro et nanotechnologies/Microélectronique. Université Paul Sabatier - Toulouse III, 1996. Français. ⟨tel-00165581⟩



Record views


Files downloads