Skip to Main content Skip to Navigation

μSpider Environnement de Conception de Réseau sur Puce

Abstract : This PhD thesis deals with interconnection design between IP cores (Intellectual Property) in a System on Chip. This work is based on an emerging infrastructure solution called Network on Chip.
The design space is wide and methodologies are required to help designer to obtain ad hoc NoC matching application requirements.
This work presents a design flow to design automatically ad hoc NoC parameters.
Clock synchronicity subject in wide chip and security concerns in NoC are also addressed.
We have developed a design tool called ìSpider. This tool is able to make choices and to configure NoC parameters according to applications constraints and needs.
Moreover, it generates the VHDL RTL code of the specified NoC.
This work has been validated on three real-life applications, a smart camera application, a telecom MC-CDMA application and a multiprocessor turbo-decoder application.
Complete list of metadata

Cited literature [73 references]  Display  Hide  Download
Contributor : Samuel Evain <>
Submitted on : Thursday, July 26, 2007 - 10:43:05 AM
Last modification on : Friday, January 8, 2021 - 3:42:50 AM
Long-term archiving on: : Thursday, April 8, 2010 - 7:08:35 PM


  • HAL Id : tel-00165436, version 1


Samuel Evain. μSpider Environnement de Conception de Réseau sur Puce. Micro et nanotechnologies/Microélectronique. INSA de Rennes, 2006. Français. ⟨tel-00165436⟩



Record views


Files downloads