Skip to Main content Skip to Navigation
Theses

Interopérabilité en émulation et prototypage matériel

Abstract : This thesis defines a new concept in RTL verification : interoperability between HDL simulators, hardware emulators and hardware prototyping platforms. The main purpose is to benefit from both good speed of hardware prototyping platforms and debug capabilities of hardware emulators and HDL simulators. To achieve this purpose, this thesis introduces the notion of design state. Then, a interoperability dedicated tool is presented. This tool add interoperability to design functionnalities. Thus, all machines working at RTL level are interoperables with each others. The main idea of interoperability is to lunch tests on fast prototyping platforms while periodically saving design state. When a bug will be faced, debug will be performed using a fast emulator or a low cost HDL simulator. The test will restart from the last database saved just before bug time. Finally, this thesis introduce a new prototyping flow which was validated on an industrial design STM HLS25.
Complete list of metadatas

Cited literature [31 references]  Display  Hide  Download

https://tel.archives-ouvertes.fr/tel-00163987
Contributor : Lucie Torella <>
Submitted on : Thursday, July 19, 2007 - 11:18:17 AM
Last modification on : Friday, December 11, 2020 - 8:28:04 AM
Long-term archiving on: : Thursday, April 8, 2010 - 8:39:52 PM

Identifiers

  • HAL Id : tel-00163987, version 1

Collections

CNRS | TIMA | UGA

Citation

A. Blampey. Interopérabilité en émulation et prototypage matériel. Micro et nanotechnologies/Microélectronique. Institut National Polytechnique de Grenoble - INPG, 2006. Français. ⟨tel-00163987⟩

Share

Metrics

Record views

203

Files downloads

1576