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Conception d'un Système Embarque Sur et Sécurisé

Abstract : This PhD researches a global methodology enabling to improve the dependability and security level against transient logic faults (natural or provoked) appearing inside a hardware/software integrated system, like for instance a smart card. Results can be applied to all systems built around a synthesisable microprocessor core and a set of specialised peripherals. The protection methods operate simultaneously and in complementary manner on hardware, application software and interface layers (most noticeably, the operating system). High level modifications have been favoured for their advantages in terms of generality, configurability, portability and perpetuity. The proposed approach aims at achieving a good trade-off between robustness and overheads, from both hardware and performance point of views. It is applied on a significant system example, representative of an embedded monoprocessor system, based on the 32-bit Leon2 processor and the eCos operating system. The processor has been modified to improve his ability to react against perturbations, by modifying its cache memories, their controllers and the integer unit pipeline. The operating system has been modified as well to implement a recovery technique based on the reutilisation of existing functions, noticeably the context switch function, in collaboration with the detection techniques applied at hardware level. A demonstrator executing representative cryptographic and image processing applications has been developed and targeted by fault injection experiments.
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Submitted on : Thursday, July 19, 2007 - 11:10:32 AM
Last modification on : Tuesday, January 26, 2021 - 9:12:04 AM
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  • HAL Id : tel-00163980, version 1




Michele Portolan. Conception d'un Système Embarque Sur et Sécurisé. Micro et nanotechnologies/Microélectronique. Institut National Polytechnique de Grenoble - INPG, 2006. Français. ⟨tel-00163980⟩



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