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Conception et test de systèmes CMOS fiables et tolérants aux pannes

Abstract : High performance ICs manufactured in deep submicron CMOS show reduced operating margins for timing, power and noise, and increased device sensitivity to contamination, size variations and cosmic ray effects. As a consequence, radiation-induced soft errors and soft failures due to small manufacturing defects that escape voltage-mode testing represent a chief concern in deep submicron CMOS. This thesis describes design and test techniques for high reliability and fault tolerance to cope with soft failures and soft errors in both commercial and safety-critical system applications. To improve the IDDQ test effectiveness in detecting soft failures, we developed highly sensitive Built-In Current (BIC) sensor designs operating at high speed and low supply voltage. Optimized IDDQ test algorithms with embedded current monitors are proposed, and synergetic effects with low power design techniques are explored. On-chip IDDQ monitoring techniques are subsequently extended to on-line testing in safety-critical CMOS system applications. An upset-tolerant static RAM design is described that uses current monitoring and parity coding for error detection and correction. Radiation test results on a prototype circuit validate this approach. In order to avoid soft error occurrence in deep submicron CMOS applications, upset-immune design techniques using technology-independent local redundancy are described and analyzed. They are validated on memory and register array prototypes using commercial 1.2, 0.8 and 0.25mm CMOS processes. On-chip test techniques are implemented for redundancy assessment of fault-tolerant CMOS architectures. Upset mechanisms in SEU-hardened CMOS storage elements are detected and analyzed using a focused pulse laser equipment, and specific design rules are devised for topology-related hardening. An upset-hardened sequential cell library has been designed in 0.6mm CMOS to be employed in an ASIC modem chip for an onboard satellite experiment.
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Contributor : Lucie Torella <>
Submitted on : Wednesday, July 18, 2007 - 2:18:42 PM
Last modification on : Friday, December 11, 2020 - 8:28:04 AM
Long-term archiving on: : Monday, September 24, 2012 - 11:15:16 AM


  • HAL Id : tel-00163765, version 1




T. Calin. Conception et test de systèmes CMOS fiables et tolérants aux pannes. Micro et nanotechnologies/Microélectronique. Institut National Polytechnique de Grenoble - INPG, 1999. Français. ⟨tel-00163765⟩



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