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Amélioration de la fiabilité des calculateurs parallèles SIMD par test et tolérance aux fautes structurelle

Abstract : With architectural and technologies advances, the way to assure electronic structures dependability becomes more and more complex. This problem is particularly crucial for structures composed of a large number of components and realized with aggressive technologies. Integrated parallel computers are such structures. They used to give high processing rate in a low volume, with a high confidence that can be put in the result. In this thesis, we propose a scheme to improve the reliability of parallel computers, based on original test and fault-tolerance schemes. In our case, the test scheme uses periodic and concurrent methods in order to permanently know the structure state. If some faulty component is found, the fault-tolerance scheme is then performed by two physical levels of reconfiguration of the structure network. We show, in the conclusion of the thesis, that with minimal and scalable hardware overhead, reliability comparable to the one of a component of the non fault-tolerant structure can be achieved.
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https://tel.archives-ouvertes.fr/tel-00163763
Contributor : Lucie Torella <>
Submitted on : Wednesday, July 18, 2007 - 2:09:14 PM
Last modification on : Friday, December 11, 2020 - 8:28:04 AM
Long-term archiving on: : Thursday, April 8, 2010 - 11:33:10 PM

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  • HAL Id : tel-00163763, version 1

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Citation

F. Clermidy. Amélioration de la fiabilité des calculateurs parallèles SIMD par test et tolérance aux fautes structurelle. Micro et nanotechnologies/Microélectronique. Institut National Polytechnique de Grenoble - INPG, 1999. Français. ⟨tel-00163763⟩

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