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Prédiction du taux d'erreurs d'architectures digitales : une méthode et des résultats expérimentaux

Abstract : This thesis aims at the study of the behavior of digital processors with respect to one of the effects of radiation environment - the Single Event Upset phenomenon, also called upset - which may modify the content of memory elements as the result of the silicon ionization resulting from the impact of charged particles. The consequences of upsets for a given application depend on both the occurrence instant and the perturbed memory element, and can go from innocuous result errors to system crashes which may provoke the loose of control of a space vehicle. As design hardening techniques cannot completely guarantee the upset immunity for circuits devoted to space applications, error rate estimation methods, based on radiation ground testing and/or in fault injection experiments, are mandatory to choose the less sensitive circuits for a given space application. The research presented in this thesis consists in the definition of a suitable method for upset-like fault injection and its experimentation for various digital architectures in order to assess its efficiency and put in evidence its capabilities. The proposed method is based on the injection of upsets in a digital board built around a processor, as the consequence of the activation of an asynchronous interruption. The execution of the instruction sequence associated with the interruption, called here CEU (Code Emulating an Upset), will provoke the modification (bit flip) of a target selected among the circuit sensitive area which comprises mainly registers and internal memory elements. The CEU injection technique was implemented using THESIC, a system dedicated to the qualification of integrated circuits under radiation. This system is composed of two digital boards (a mother board and a daughter board) whose configuration revealed as being well adapted to constraints imposed by the studied fault injection approach. Demonstrating that application error rates can be predicted from the results of CEU injection experiments combined with the measure of individual sensitivities to upsets of the processor's memory elements obtained from radiation testing. The confrontation for different architectures and programs, of predicted error rates to measured ones proved the validity of the approach.
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Submitted on : Tuesday, July 17, 2007 - 3:51:04 PM
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  • HAL Id : tel-00163484, version 1




S. Rezgui. Prédiction du taux d'erreurs d'architectures digitales : une méthode et des résultats expérimentaux. Micro et nanotechnologies/Microélectronique. Institut National Polytechnique de Grenoble - INPG, 2001. Français. ⟨tel-00163484⟩



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