Verification of RTL generated from scheduled behavior in a high-level synsthesis flow, Proc. International Conference on Computer-Aided Design (ICCAD), 1998. [Ack54] W. Ackermann. Solvable Cases of the Decision Problem. Studies in Logic and the Foundations of Mathematics, 1954. ,
Using complete-1-distinguish- ability for FSM equivalence checking, Proc. International Conference on Computer-Aided Design (ICCAD), 1996. ,
DOI : 10.1109/iccad.1996.569807
Formal verification of iterative algorithms in microprocessors, Proceedings of the 37th conference on Design automation , DAC '00 ,
DOI : 10.1145/337292.337388
A Methodology for Large-Scale Hardware Verification ,
DOI : 10.1007/3-540-40922-X_17
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.302.2736
Combining theorem proving and trajectory evaluation in an industrial environment, Proceedings of the 35th annual conference on Design automation conference , DAC '98, 1998. ,
DOI : 10.1145/277044.277189
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.31.6108
Formal verification using parametric representations of Boolean constraints, Proc ,
DOI : 10.1145/309847.309968
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.409.8282
Formally verifying a microprocessor using a simulation methodology, Proceedings of the 31st annual conference on Design automation conference , DAC '94, 1994. ,
DOI : 10.1145/196244.196575
COS- MOS: A compiled simulator for MOS circuits, Proc. ACM/IEEE Design Automation Conference (DAC), 1987. ,
Formal hardware verification by symbolic ternary trajectory evaluation, Proceedings of the 28th conference on ACM/IEEE design automation conference , DAC '91 ,
DOI : 10.1145/127601.127701
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.106.3160
Verification of arithmetic functions with binary moment diagrams, 1994. ,
Verification of arithmetic circuits with binary moment diagrams, Proceedings of the 32nd ACM/IEEE conference on Design automation conference , DAC '95, 1995. ,
DOI : 10.1145/217474.217583
Symbolic model checking for sequential circuit verification, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.13, issue.4, pp.401-424, 1994. ,
Sequential circuit verification using symbolic model checking, Conference proceedings on 27th ACM/IEEE design automation conference , DAC '90 ,
DOI : 10.1145/123186.123223
Automatic verification of pipelined microprocessor control, Proc. Computer Aided Verification (CAV), 1994. ,
DOI : 10.1007/3-540-58179-0_44
Validity checking for combinations of theories with equality, Proc. Formal Methods in Computer-Aided Design (FMCAD), volume 1166 of LNCS, 1996. ,
DOI : 10.1007/BFb0031808
A decision procedure for bit-vector arithmetic, Proceedings of the 35th annual conference on Design automation conference , DAC '98, 1998. ,
DOI : 10.1145/277044.277186
Cycle-based symbolic simulation of gate-level synchronous circuits, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361), 1999. ,
DOI : 10.1109/DAC.1999.781347
The effects of false paths in high-level synthesis, Proc. International Conference on Computer-Aided Design (ICCAD), 1991. ,
Verifying pipelined hardware using symbolic logic simulation, Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1989. ,
DOI : 10.1109/ICCD.1989.63359
Exploiting Positive Equality in a Logic of Equality with Uninterpreted Functions, Proc. Computer Aided Verification (CAV), volume 1633 of LNCS, 1999. ,
DOI : 10.1007/3-540-48683-6_40
The FM9001 microprocessor proof, 1994. ,
ACL2 theorems about commercial microprocessors, Proc. Formal Methods in Computer- Aided Design (FMCAD), volume 1166 of LNCS, 1996. ,
DOI : 10.1007/BFb0031816
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.28.2678
Formal verification of register binding, Proc. Workshop on Advances in Verification (Wave'2000), 2000. ,
Proving Theorems about LISP Functions, Journal of the ACM, vol.22, issue.1, pp.129-144, 1975. ,
DOI : 10.1145/321864.321875
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.51.4270
A computational logic, 1979. ,
A computational logic handbook, 1997. ,
Formal methods URL: http://archive.comlab.ox.ac.uk/formal-methods.html. Centre for Applied Formal Methods, 2000. ,
Formale Verifikation der Register-Allokation, Proc. ITG/GI/GMM-Workshop, 2000. ,
Symbolic verification of MOS circuits, Proc. Chapel Hill Conference on VLSI, pp.419-438, 1985. ,
Graph-based algorithms for boolean function manipulation, IEEE Transactions on Computers, issue.8, pp.35677-691, 1986. ,
Symbolic simulation -techniques and applications, Proc. ACM/IEEE Design Automation Conference (DAC), 1990. ,
Verification of synchronous circuits by symbolic logic simulation, Hardware Specification, Verification, and Synthesis: Mathematical Aspects, pp.14-24, 1990. ,
Techniques for verifying superscalar microprocessors ,
Verification of sequential machines using Boolean functional vectors, Proc. IFIP International Workshop on Applied Formal Methods for Correct VLSI Design, 1989. ,
Verification of synchronous sequential machines based on symbolic execution, Proc. Automatic Verification Methods for Finite State Systems, 1989. ,
Formal Boolean manipulations for the verification of sequential machines, Proceedings of the European Design Automation Conference, 1990., EDAC., 1990. ,
DOI : 10.1109/EDAC.1990.136620
Computing timed transition relations for sequential cycle-based simulation, Proc. Design, Automation and Test in Europe Conference (DATE), 1999. ,
Symbolic Simulation for Correct Machine Design, 16th Design Automation Conference, 1979. ,
DOI : 10.1109/DAC.1979.1600119
On Shostak's decision procedure for combinations of theories, IEEE International Conference on Automated Deduction (CADE), volume 1104 of LNAI, 1996. ,
DOI : 10.1007/3-540-61511-3_107
An efficient decision procedure for the theory of fixed-size bit-vectors, Proc. Computer Aided Verification (CAV), volume 1254 of LNCS, 1997. ,
Symbolic simulation for functional verification with ADLIB and SDL, Proc. ACM/IEEE Design Automation Conference (DAC), 1981. ,
VEGA: a verification tool based on genetic algorithms, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273), 1998. ,
DOI : 10.1109/ICCD.1998.727069
Approximate equivalence verification of sequential circuits via genetic algorithms, Proc. Design, Automation and Test in Europe Conference (DATE), 1999. ,
Formal methods: state of the art and future directions, ACM Computing Surveys, vol.28, issue.4, 1996. ,
DOI : 10.1145/242223.242257
URL : https://hal.archives-ouvertes.fr/hal-00444076
The application of program verification techniques to hardware verification, Proc. ACM/IEEE Design Automation Conference (DAC), 1979. ,
Applications of Symbolic Execution to Program Testing, Computer, vol.11, issue.4, pp.51-60, 1978. ,
DOI : 10.1109/C-M.1978.218139
Characterizing correctness properties of parallel programs using fixpoints, Automata, Languages and Programming, 1980. ,
DOI : 10.1007/3-540-10003-2_69
Formally correct construction of pipelined processors, 1998. ,
Automatic verification of scheduling results in high-level synthesis, Proc. Design, Automation and Test in Europe Conference (DATE), 1999. ,
The SMAX internal data structure, 1992. ,
Enhancing simulation with BDDs and ATPG, Proc. ACM/IEEE Design Automation Conference (DAC), 1999. ,
DOI : 10.1145/309847.309965
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.27.8716
Introduction to HOL: a theorem proving environment for higher-order logic, 1993. ,
Toward formalizing a validation methodology using simulation coverage, Proc. ACM/IEEE Design Automation Conference (DAC), 1997. ,
DOI : 10.1145/266021.266359
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.32.1639
Symbolic simulation of the JEM1 microprocessor, Proc. Formal Methods in Computer-Aided Design (FMCAD), volume 1522 of LNCS, 1998. ,
Formal synthesis for pipeline design, Proc. DMTCS+CATS'99 number 3 of Australian Computer Science Communications, pp.247-261, 1999. ,
Formally correct construction of a pipelined DLX architecture, 1998. ,
Language of Labelled Segments documentation, 1998. ,
Ein transformativer Ansatz für die Synthese und Verifikation algorithmischer Hardwarebeschreibungen, 2000. ,
An Introduction to Proving the Correctness of Programs, ACM Computing Surveys, vol.8, issue.3, pp.331-353, 1976. ,
DOI : 10.1145/356674.356677
Implementation of a multiple-domain decision diagram package, Proc. Advanced Research Working Conference on Correct Hardware Design and Verification Methods (CHARME), 1997. ,
Hybrid graph manipulation package demo, 1998. ,
Effiziente Konstruktion und Manipulation von binären Entscheidungsgraphen, 1999. ,
Computer architecture: a quantitative approach, 1996. ,
Automatische Synthese und Verifikation von RISC-Prozessoren, Proc. GI/ITG/GMM Workshop, 1999. ,
False-path elimination and simplification of sequential acyclic descriptions with complex branching logic, Proc. Workshop on Algorithm Architecture Adequation (AAA), 2000. ,
Symbolic trajectory evaluation, Formal Hardware Verification. Methods and Systems in Comparison, 1997. ,
DOI : 10.1007/3-540-63475-4_1
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.48.2326
Decomposing the proof of correctness of pipelined microprocessors, Proc. Computer Aided Verification (CAV), volume 1427 of LNCS, 1998. ,
DOI : 10.1007/BFb0028739
Proof of Correctness of a Processor with Reorder Buffer Using the Completion Functions Approach, Proc. Computer Aided Verification (CAV), volume 1633 of LNCS, 1999. ,
DOI : 10.1007/3-540-48683-6_7
State reduction using reversible rules, Proc. ACM/IEEE Design Automation Conference (DAC), 1996. ,
Efficient validity checking for processor verification, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD), 1995. ,
DOI : 10.1109/ICCAD.1995.479877
Some techniques for efficient symbolic simulation-based verification, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors, 1992. ,
DOI : 10.1109/ICCD.1992.276218
Reducing Manual Abstraction in Formal Verification of Out- of- Order Execution, Proc. Formal Methods in Computer-Aided Design (FMCAD), volume 1522 of LNCS, 1998. ,
DOI : 10.1007/3-540-49519-3_2
Formal verification in hardware design: a survey, ACM Transactions on Design Automation of Electronic Systems, vol.4, issue.2, 1999. ,
DOI : 10.1145/307988.307989
A new approach to program testing. SIGPLAN Notices, Proc. International Conference on Reliable Software, pp.228-233, 1975. ,
Symbolic execution and program testing, Communications of the ACM, vol.19, issue.7, pp.385-394, 1976. ,
An industrial strength theorem prover for a logic based on Common Lisp, IEEE Transactions on Software Engineering, vol.23, issue.4, pp.203-213, 1997. ,
DOI : 10.1109/32.588534
¨ Ubersetzer für C in eine Beschreibungssprache für erweiterte Zustandsdiagramme Master's thesis Olukotun. A scalable formal verification methodology for pipelined microprocessors, Proc. ACM/IEEE Design Automation Conference (DAC), 1996. ,
Verifying correct pipeline implementation for microprocessors, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97, 1997. ,
DOI : 10.1109/ICCAD.1997.643402
Symbolic simulation: an ACL2 approach, Proc. Formal Methods in Computer-Aided Design (FMCAD), volume 1522 of LNCS, 1998. ,
Simplification by Cooperating Decision Procedures, ACM Transactions on Programming Languages and Systems, vol.1, issue.2, pp.245-257, 1979. ,
DOI : 10.1145/357073.357079
Fast Decision Procedures Based on Congruence Closure, Journal of the ACM, vol.27, issue.2, pp.356-364, 1980. ,
DOI : 10.1145/322186.322198
PVS: A prototype verification system, IEEE International Conference on Automated Deduction (CADE), p.of LNAI, 1992. ,
DOI : 10.1007/3-540-55602-8_217
Formal verification for fault-tolerant architectures: Prolegomena to the design of PVS, IEEE Transactions on Software Engineering, vol.21, issue.2, pp.107-125, 1995. ,
Formally verifying IEEE compilance of floating-point hardware, Intel Technology Journal, First Quarter, 1999. ,
Exploiting symmetry when verifying transistor-level circuits by symbolic trajectory evaluation, See also (same authors/title) Proc. Computer Aided Verification (CAV), pp.918-935, 1997. ,
DOI : 10.1109/43.771176
Formal verification of content addressable memories using symbolic trajectory evaluation, Proc. ACM/IEEE Design Automation Conference (DAC), 1997. ,
Formal verification of PowerPC arrays using symbolic trajectory evaluation, 33rd Design Automation Conference Proceedings, 1996 ,
DOI : 10.1109/DAC.1996.545655
Formal Verification of Designs with Complex Control by Symbolic Simulation, Proc. Advanced Research Working Conference on Correct Hardware Design and Verification Methods (CHARME), volume 1703 of LNCS, 1999. ,
DOI : 10.1007/3-540-48153-2_18
Formal Verification of Descriptions with Distinct Order of Memory Operations, Proc. ASIAN'99, 1999. ,
DOI : 10.1007/3-540-46674-6_26
Sequential equivalence checking by symbolic simulation ,
Formulation and evaluation of scheduling techniques for control flow graphs, Proceedings of EURO-DAC. European Design Automation Conference, 1995. ,
DOI : 10.1109/EURDAC.1995.527434
URL : https://hal.archives-ouvertes.fr/hal-00008139
Formal verification by symbolic evaluation of partially-ordered trajectories, Formal Methods in System Design, vol.6, issue.No. 5, pp.147-189, 1995. ,
DOI : 10.1007/BF01383966
Using magnetic disk instead of main memory in the Mur ? verifier, Proc. Computer Aided Verification (CAV), volume 1427 of LNCS, 1998. ,
A practical decision procedure for arithmetic with function symbols, Journal of the ACM, vol.26, issue.2, pp.351-360, 1979. ,
Deciding combinations of theories, Journal of the ACM, vol.31, issue.1, pp.1-12, 1984. ,
Formal verification of out-of-order execution using incremental flushing, Proc. Computer Aided Verification (CAV), volume 1427 of LNCS, 1998. ,
DOI : 10.1007/BFb0028737
Applying formal verification to a commercial microprocessor, IFIP International Conference on Computer Hardware Description Languages, 1995. ,
Formal verification of the AAMP5 microprocessor: a case study in the industrial use of formal methods, Workshop on industrial-strength formal specification techniques (WIFT), pp.2-16, 1995. ,
Optimierung eines Verfahrens zur formalen¨Aquivalenzformalen¨ formalen¨Aquivalenzprüfung von Prozessorbeschreibungen, 1998. ,
Bit-level abstraction in the verification of pipelined microprocessors by correspondence checking, Proc. Formal Methods in Computer-Aided Design (FMCAD), volume 1522 of LNCS, 1998. ,
Exploiting postive equality and partial non-consistency in the formal verification of pipelined microprocessors, Proc. ACM/IEEE Design Automation Conference (DAC), 1999. ,
Superscalar processor verification using efficient reductions of the logic of equality with uninterpreted functions to propositional logic, Proc. Advanced Research Working Conference on Correct Hardware Design and Verification Methods (CHARME), volume 1703 of LNCS, 1999. ,
Formal verification of superscalar processors with multicycle functional units, exceptions, and branch prediction, Proc. ACM/IEEE Design Automation Conference (DAC), 2000. ,
Automatic generation of assertions for formal verification of PowerPC T M microprocessor arrays using symbolic trajectory evaluation, Proc ,
Mechanically checking a lemma used in an automatic verification tool, Proc. Formal Methods in Computer-Aided Design (FMCAD), volume 1166 of LNCS, 1996. ,
DOI : 10.1007/BFb0031821
Symbolic Simulation with Approximate Values, Proc. Formal Methods in Computer-Aided Design (FMCAD), 1954. ,
DOI : 10.1007/3-540-40922-X_29
Sequential Equivalence Checking by Symbolic Simulation ,
DOI : 10.1007/3-540-40922-X_26
URL : https://hal.archives-ouvertes.fr/tel-00163429
Formal Verification of Designs with Complex Control by Symbolic Simulation, Proc. Advanced Research Working Conference on Correct Hardware Design and Verification Methods (CHARME), volume 1703 of LNCS, 1999. ,
DOI : 10.1007/3-540-48153-2_18
Formal Verification of Descriptions with Distinct Order of Memory Operations, Proc. ASIAN'99, 1999. ,
DOI : 10.1007/3-540-46674-6_26
Formale Verifikation automatisch generierter Pipelinesysteme durch symbolische Simulation, Proc. 9. Entwurf Integrierter Schaltungen (EIS) Workshop. Darmstadt, 1999. ,
Automatic verification of scheduling results in high-level synthesis, Proc. Design, Automation and Test in Europe Conference (DATE), 1999. ,
Formal synthesis for pipeline design, Proc. DMTCS+CATS'99 number 3 of Australian Computer Science Communications, pp.247-261, 1999. ,
Formale Verifikation der Register-Allokation, Proc. ITG/GI, 2000. ,
False-path elimination and simplification of sequential acyclic descriptions with complex branching logic, Proc. Workshop on Algorithm Architecture Adequation (AAA) BIBLIOGRAPHY [Rit00b] G. Ritter. Vérification formelle dans la synthèse automatique des systèmes avec pipeline Proc. JNRDM-Workshop, 2000. ,
Automatische Synthese und Verifikation von RISC-Prozessoren, Proc. GI/ITG/GMM Workshop, 1999. ,
Functional description and macro architecture of an industrial viterbi decoder (20 pp.), 1999. ,
Formally correct construction of pipelined processors, 1998. ,
Der Einsatz risikoadjustierter Kalkulationszinsfüße bei Investitionsentscheidungen, Betriebswirtschaftliche Forschung und Praxis BFuP (journal), vol.49, issue.5, pp.593-612, 1997. ,
in Frankfurt/Main Nationality German Marital Status Married, one child Foreign Languages English, French (fluently) Academic Qualifications Sep 1998 until present Combined bi-national PhD with TIMA Laboratory, 1969. ,