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Test en ligne des systèmes digitaux linéaires

Abstract : The linear digital systems represent an important class of circuits used in several critical application missions. Therefore the on-line fault detection problem in linear digital systems is very important where errors in processing data, during normal operation, can lead to catastrophic effects. In this work, we purpose a new method for concurrent fault (error) detection in linear digital systems. The proposed fault detection scheme is based on analytical redundancy describing the relationships among the histories of the system input and output. The developed algorithms allow to design robust fault detection detectors, i.e. detectors that have high sensitivity to faults and low sensitivity to the systems noise (the noise generated within the systems is not considered as faults and have to be tolerated). The hardware of the supplementary circuitries needed to implement the on-line fault detection function is still very reasonable. In contrast of all other fault detection methods dealing with specific problems, the proposed technique is general applicable to all linear digital systems. The parameters as well as the VHDL description model of the fault detection circuitry for every linear digital system can be generated automatically by means of software tool developed during the thesis.
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Contributor : Lucie Torella <>
Submitted on : Tuesday, July 17, 2007 - 2:41:01 PM
Last modification on : Friday, December 11, 2020 - 8:28:04 AM
Long-term archiving on: : Thursday, April 8, 2010 - 11:28:20 PM


  • HAL Id : tel-00163415, version 1




A. Abdelhay. Test en ligne des systèmes digitaux linéaires. Micro et nanotechnologies/Microélectronique. Institut National Polytechnique de Grenoble - INPG, 2001. Français. ⟨tel-00163415⟩



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