U. Chier and V. Du-ltre-peut, etre g en erer : 1. L'horloge fonctionnel du ltre 2. L'entr ee du multiplieur avant son aaectation par la faute 3. La localisation du bit aaect e : Z p a s de faute, pp.1-1

. La-signature-de-la-r-eponse-du-multiplieur-9, La signature correcte 10

A. Abdelhay, Test en Ligne des Syst emes Digitaux Lin eaires, 2001.

A. Abdelhay, E. Simeu, I. Sakho, and M. A. , A robust fault detection scheme for concurrent testing of linear digital systems, 6th African Conference o n R esearch in Computer Science, 2002.
URL : https://hal.archives-ouvertes.fr/hal-00015846

M. Abramovici, M. A. Breuer, A. D. Friedman, W. H. Freeman, and C. , Digital Systems testing & Testable Design, An imprint o f W . H . F reeman and Company, 1990.
DOI : 10.1109/9780470544389

V. D. Agrawal and K. Cheng, Finite state machine synthesis with embedded test function, Journal of Electronic Testing, vol.22, issue.3, pp.221-228, 1990.
DOI : 10.1007/BF00938685

A. Antola, F. Ferrandi, V. Piuri, and M. Sami, Semiconcurrent error detection in data paths, IEEE Transactions on Computers, vol.50, issue.5, pp.449-465, 2001.
DOI : 10.1109/12.926159

D. F. Bacon, S. L. Graham, and O. J. Sharp, Compiler transformations for high-performance computing, ACM Computing Surveys, vol.26, issue.4, pp.345-420, 1994.
DOI : 10.1145/197405.197406

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.114.4215

P. H. Bardell, Built-In Test for VLSI Pseudorandom techniques, 1987.

M. Bellanger, Traitement num erique du signal. Th eiorie et pratique, 1987.

E. Berrebi, Combined control ow and data ow domonated high-level synthesis, 33rd Design Automation Conference, pp.573-578, 1996.

S. Bhattacharya, P. K. Murthy, and E. A. Lee, Synthesis of embeddedsoftware from synchronous dataaow speciications, The Journal of VLSI Signal Processing, vol.21, issue.2, pp.151-166, 1999.
DOI : 10.1023/A:1008052406396

G. Blanchet and P. Devriendt, Processeurs de traitement num erique du signal(dsp) Techniques de l'ingenieur

S. Brown, Fpga architectural research: A s y r v ey, IEEE Design & Test of Computers, 1996.
DOI : 10.1109/54.544531

S. Brown and J. Rose, FPGA and CPLD architectures: a tutorial, IEEE Design & Test of Computers, vol.13, issue.2, pp.42-57, 1996.
DOI : 10.1109/54.500200

R. Camposano, Behavioral synthesis, 33rd Design Automation Conference, pp.33-34, 1996.

J. E. Carletta and C. Papachristou, Behavioral testability insertion for datapath/controller circuits, Journal of Electronic Testing: Theory and Applications, issue.11, pp.9-28, 1997.

V. Chaiyakul, D. D. Gajski, and L. Ramachandran, High-level transformations for minimizing syntactic variances, Proceedings of the 30th international on Design automation conference , DAC '93, pp.413-418, 1993.
DOI : 10.1145/157485.164956

L. Chao, A. Lapaugh, E. H. , and -. Sha, Rotation scheduling, Proceedings of the 30th international on Design automation conference , DAC '93, pp.566-572, 1993.
DOI : 10.1145/157485.165042

A. Chatterjee and R. K. Roy, An architectural transformation program for optimization of digital systems by multi-level decomposition, Proceedings of the 30th international on Design automation conference , DAC '93, pp.343-348, 1993.
DOI : 10.1145/157485.164923

C. Chen and D. G. Saab, A novel behavioral testability measure, IEEE Transactions on Computer-Aided Design of integrated circuits and systems, vol.12, issue.12, 1993.

Y. H. Choi and M. Malek, A tolerant t t p r o c e s s o r, Proceedings of the fault tolerant computing symposium, pp.266-271, 1985.

J. Cong and Y. Ding, On area/depth trade-oo in lut-based fpga technology mapping, 30th Design Automation Conference, pp.213-218, 1993.

A. Dammak, Etude de M esures de Testabilit e de Syst emes Logiques. Universit e d e P aris-sud, Centre d, 1985.

R. David, Random Testing of Digital Circuits, 1998.

L. Davis, Handbook of Genetic Algorithms, 1991.

S. Devadas, H. T. Ma, and A. R. Newton, Redundancies and don't cares in sequential logic synthesis, Journal of Electronic Testing: Theory and Applications, issue.1, pp.15-30, 1990.

M. K. Dhodhi, I. Ahmad, and A. A. , High-level synthesis of data paths for easy testability, IEE Proceedings - Circuits, Devices and Systems, vol.142, issue.4, pp.209-216, 1995.
DOI : 10.1049/ip-cds:19952011

E. Dieulesait and D. Royer, Syst emes lin eaires de commande a signaux echantillonn es, 1990.

R. Dorsch and H. Wunderlich, Accumulator based deterministic BIST, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270), pp.412-421, 1998.
DOI : 10.1109/TEST.1998.743181

P. Duncan, K. Kindsfater, L. Lynette, and J. Rajeev, Strategies for design automation of high speed digital filters, Journal of VLSI signal processing systems for signal, image and video technology, vol.220, issue.no. 4598, pp.105-119, 1995.
DOI : 10.1007/BF02406473

M. L. Flottes, D. Hammad, and R. B. , Automatic synthesis of bisted data paths from high level speciication, European Design and Test Conference, pp.591-598, 1994.

M. L. Flottes, D. Hammad, and B. Rouzeyre, Improving testability of non-scan design during behavioral synthesis, Journal of Electronic Testing: Theory and Applications, issue.11, pp.29-42, 1997.

S. Freeman, Test generation for data-path logic: the F-path method, IEEE Journal of Solid-State Circuits, vol.23, issue.2, pp.421-427, 1988.
DOI : 10.1109/4.1002

I. Ghosh and N. K. Jha, High-level test synthesis: a survey, Integration, the VLSI Journal, vol.26, issue.1-2, pp.79-99, 1998.
DOI : 10.1016/S0167-9260(98)00022-4

J. C. Gille and M. Clique, Syst emes lin eaires, equations d' etat, 1990.

G. Goossens, Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures, Journal of VLSI signal processing systems for signal, image and video technology, vol.9, issue.no. 1???2, pp.49-65, 1995.
DOI : 10.1007/BF02406470

L. Guerra, M. Potkonjak, and J. Rabaey, A methodology for guided behavioral-level optimization, Proceedings of the 35th annual conference on Design automation conference , DAC '98, pp.309-314, 1998.
DOI : 10.1145/277044.277134

R. W. Hamming, Error detecting and error correcting codes. The Bell System Technical Journal, pp.147-160, 1950.
DOI : 10.1002/j.1538-7305.1950.tb00463.x

URL : http://campus.unibo.it/10913/1/hamming1950.pdf

I. G. Harris and A. Orailoo-glu, Microarchitectural synthesis of VLSI designs with high test concurrency, Proceedings of the 31st annual conference on Design automation conference , DAC '94, pp.206-211, 1994.
DOI : 10.1145/196244.196353

R. L. Haupt and S. E. Haupt, Practical Genetic Algorithms, 1998.
DOI : 10.1002/0471671746

M. Haworth and W. P. Birmingham, Towards optimal system-level design, Proceedings of the 30th international on Design automation conference , DAC '93, pp.434-437, 1993.
DOI : 10.1145/157485.164965

I. Hong, D. Kirovski, and M. Potkonjak, Potential-driven statistical ordering of transformations, Proceedings of the 34th annual conference on Design automation conference , DAC '97, pp.347-352, 1997.
DOI : 10.1145/266021.266161

S. H. Hou, N. Ansari, and H. Ren, A genetic algorithm for multiprocessor scheduling, IEEE Transactions on Parallel and Distributed Systems, vol.5, issue.2, pp.113-120, 1994.
DOI : 10.1109/71.265940

D. Houzet, Microprocesseurs. approche g en erale, E3, vol.550, pp.1-17, 1998.

D. Houzet and R. J. Chevance, Microprocesseurs : Architecture et performances, E3, vol.555, pp.3-4, 1998.

S. H. Huang, A tree-based scheduling algorithm for control-dominated circuits, Proceedings of the 30th international on Design automation conference , DAC '93, pp.578-582, 1993.
DOI : 10.1145/157485.165051

J. Huisken and F. Welten, FADIC, Proceedings of the 33rd annual conference on Design automation conference , DAC '96, pp.579-584, 1996.
DOI : 10.1145/240518.240628

E. C. Ifeachor and B. W. Jervis, Digital Signal Processing A P r actical Approach, 1993.

M. Inoue and H. Fujiwara, An approach t o t e s t s y n thesis from higher level. INTEGRATION, the VLSI journal, pp.101-116, 1998.

Z. Iqbal, M. Potkonjak, and A. Parker, Critical path minimization using retiming and algebraic speed-up, Proceedings of the 30th international on Design automation conference , DAC '93, pp.573-577, 1993.
DOI : 10.1145/157485.165046

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.64.965

A. A. Ismaeel, R. Bhatnagar, and R. Mathew, Modiication of scheduled data ow graph for on-line testability, Microelectronics Reliability, issue.39, pp.1473-1484, 1999.

R. Karri and N. Mukherjee, Versatile BIST: an integrated approach to on-line/off-line BIST, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270), pp.910-917, 1998.
DOI : 10.1109/TEST.1998.743283

R. Karri and A. Orailoo-glu, High-level synthesis of fault-secure microarchitectures, Proceedings of the 30th international on Design automation conference , DAC '93, pp.429-433, 1993.
DOI : 10.1145/157485.164963

D. W. Kenneth and S. Dea, High-level synthesis for testability: A survey and perspective, 33rd Design Automation Conference, pp.131-136, 1996.

G. Kiefer and H. Wunderlich, Deterministic BIST with multiple scan chains, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270), pp.1057-1064, 1998.
DOI : 10.1109/TEST.1998.743304

H. B. Kim, T. Takahashi, and D. S. Ha, Test session oriented built-in self-testable data path synthesis, Proceedings of the ITC 98, pp.154-163, 1998.

D. C. Ku and G. Micheli, Relative scheduling under timing constraints: algorithms for high-level synthesis of digital circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.11, issue.6, pp.696-717, 1992.
DOI : 10.1109/43.137516

D. M. Kwai and B. Parhami, Scalability of programmable r digital lters, The Journal of VLSI Signal Processing, vol.21, issue.1, pp.31-35, 1999.
DOI : 10.1023/A:1008023605124

Y. K. Kwok and I. Ahmad, Efficient Scheduling of Arbitrary Task Graphs to Multiprocessors Using a Parallel Genetic Algorithm, Journal of Parallel and Distributed Computing, vol.47, issue.1, pp.58-77, 1997.
DOI : 10.1006/jpdc.1997.1395

Y. Kwok and I. Ahmad, Static scheduling algorithms for allocating directed task graphs to multiprocessors, ACM Computing Surveys, vol.31, issue.4, pp.406-471, 1999.
DOI : 10.1145/344588.344618

S. Laha and J. H. Patel, Error detecting in arithmetic operations using time redundancy, Proceedings of the fault tolerant computing symposium, pp.298-305, 1983.

E. A. Lee and D. G. Messerschmitt, Static scheduling of synchronous data ow programs for digital signal processing, IEEE Transactions on Computers, issue.1, pp.3624-3659, 1987.

M. T. Lee, Domaine-speciic high-level modeling and synthesis for atm swith design using vhdl, 33rd Design Automation Conference, pp.585-590, 1996.

T. Lee, N. K. Jha, and W. H. Wolf, Behavioral synthesis of highly testable data paths under the non-scan and partial scan environments, Proceedings of the 30th international on Design automation conference , DAC '93, pp.292-297, 1993.
DOI : 10.1145/157485.164897

T. Lee, W. H. Wolf, and N. K. Jha, Behavioral synthesis for easy testability in data path scheduling, IEEE/ACM International Conference on Computer-Aided Design, pp.616-619, 1992.
DOI : 10.1109/ICCAD.1992.279303

J. Lefermann, Syst emes lin eaires, variables d' etat, 1972.

J. Li and R. K. Gupta, HDL optimization using timed decision tables, Proceedings of the 33rd annual conference on Design automation conference , DAC '96, pp.51-54, 1996.
DOI : 10.1145/240518.240528

A. Majumdar, R. Jain, and K. Saluja, Incorporating testability considerations in high-level synthesis, Journal of Electronic Testing: Theory and Applications, issue.5, pp.43-55, 1994.

A. Majumdar, R. Jain, and K. Saluja, Incorporating performance and testability constraints during binding in high-level synthesis, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.15, issue.10, pp.1212-1225, 1996.
DOI : 10.1109/43.541441

S. Malik, E. M. Sentovich, and R. K. Brayton, Retiming and resynthesis: optimizing sequential networks with combinational techniques, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.10, issue.1, pp.74-84, 1991.
DOI : 10.1109/43.62793

P. Mazumder and E. M. Rudnick, Genetic Algorithms for VLSI design, Layout and test Automation, 1999.

M. C. Mcfarland, A. C. Parker, and R. Camposano, The high-level synthesis of digital systems, Proceedings of the IEEE, vol.78, issue.2, pp.301-318, 1990.
DOI : 10.1109/5.52214

M. Mehendale, MIM, Proceedings of the 30th international on Design automation conference , DAC '93, pp.219-223, 1993.
DOI : 10.1145/157485.164678

M. Mehendale, G. Venkatesh, and S. D. Sherlekar, Optimized code generation of multiplication-free linear transforms, 33rd Design Automation Conference, pp.41-46, 1996.

H. C. Mike, A testability measure for hierarchical design environnements, IEEE ETC, 1995.

P. Monteiro and T. R. Rao, A residue checker for arithmetic and logical operations, Proceedings of the fault tolerant computing symposium, pp.8-13, 1972.

N. Mukherjee, J. Rajski, and J. Tyszer, Testing schemes for FIR filter structures, IEEE Transactions on Computers, vol.50, issue.7, pp.674-688, 2001.
DOI : 10.1109/12.936234

R. Murgai, R. K. Brayton, and A. Sangiovanni-vincentelli, Sequential synthesis for table look up programmable gate arrays, Proceedings of the 30th international on Design automation conference , DAC '93, pp.224-229, 1993.
DOI : 10.1145/157485.164681

M. A. Naal and E. Simeu, Mesure de testabilit e pour la synth ese de haut niveau, Colloque CAO d e Circuits Int egr es et Syst emes, 1999.

M. A. Naal and E. Simeu, High level synthesis methodology for on-line testability optimization, Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646), pp.201-206, 2000.
DOI : 10.1109/OLT.2000.856637

URL : https://hal.archives-ouvertes.fr/hal-00015849

M. A. Naal and E. Simeu, Using concurrent and semi-concurrent on-line testing during high level synthesis: an adaptable approach, Proceedings of the 8th IEEE IOLTW02, 2002.

J. V. Neumann, Probabilistic Logics and the Synthesis of Reliable Organisms From Unreliable Components, Automata Studies Annals of Mathematical Studies, issue.43, pp.43-98, 1956.
DOI : 10.1515/9781400882618-003

A. Orailoo-glu and I. G. Harris, Microarchitectural synthesis for rapid BIST testing, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.16, issue.6, pp.573-586, 1997.
DOI : 10.1109/43.640616

C. A. Papachristou, S. Chiu, and H. Harmanani, A data path synthesis method for selftestable designs, 28th Design Automation Conference, pp.378-348, 1991.

K. Parhi, High-level algorithm and architecture transformations for DSP synthesis, Journal of VLSI signal processing systems for signal, image and video technology, vol.20, issue.No. 7, pp.121-143, 1995.
DOI : 10.1007/BF02406474

I. Parulkar, S. K. Gupta, and M. A. Breuer, Lower bounds on test resources for scheduled data ow graphs, 33rd Design Automation Conference, pp.143-148, 1996.

P. G. and J. P. Knight, Force-directed scheduling for the behavioral synthesis of asic's, IEEE Transactions on Computer-Aided Design, vol.8, issue.6, pp.661-679, 1989.

P. G. Paulin, C. Liem, T. C. May, and S. Sutarwala, DSP design tool requirements for embedded systems: A telecommunications industrial perspective, Journal of VLSI signal processing systems for signal, image and video technology, vol.23, issue.1-2, pp.23-47, 1995.
DOI : 10.1007/BF02406469

J. L. Pino, S. Ha, E. A. Lee, and J. T. Buck, Software synthesis for DSP using ptolemy, Journal of VLSI signal processing systems for signal, image and video technology, vol.7, issue.no. 2, pp.7-21, 1995.
DOI : 10.1007/BF02406468

D. K. Pradhan and S. M. Reddy, A design technique for synthesis of fault tolerant adders, Proceedings of the fault tolerant computing symposium, pp.20-23, 1972.

L. R. Rabiner and B. Gold, Theory and applicqtion of digital signal processing, 1975.

G. Russell and I. L. Sayers, Advanced Simulation and Test Methodology for VLSI design, 1989.

P. Wkar and D. Thomas, Performance directed technology mapping for look up table based fpgas, 30th Design Automation Conference, pp.208-212, 1993.

A. Seawright and F. Brewer, High-level symbolicconstruction techniques for high performance sequential synthesis, 30th Design Automation Conference, pp.424-428, 1993.

A. Sharma and R. Jain, Estimating architectural resources and performance for high-leval synthesis applications, 30th Design Automation Conference, pp.424-428, 1993.
DOI : 10.1145/157485.164929

A. Sharma and R. Jain, InSyn, Proceedings of the 30th international on Design automation conference , DAC '93, pp.349-354, 1993.
DOI : 10.1145/157485.164926

U. N. Shenoy, P. Banerjee, and A. Choudhary, A system-level synthesis algorithm with guaranteed solution quality, Proceedings of the conference on Design, automation and test in Europe , DATE '00, 2000.
DOI : 10.1145/343647.343812

D. P. Siewiorek and E. J. Mccluskey, An Iterative Cell Switch Design for Hybrid Redundancy, IEEE Transactions on Computers, vol.22, issue.3, pp.290-297, 1973.
DOI : 10.1109/T-C.1973.223709

E. Simeu, Test Al eatoire : evaluation de la testabilit e des circuits combinatoires, 1992.

E. Simeu, A. Abdelhay, and M. A. , Robust concurrent self test of linear digital systems. The 10th Anniversary Compendium of Papers from Asian Test Symposium, 2001.
URL : https://hal.archives-ouvertes.fr/hal-00015844

E. Simeu, A. Abdelhay, and M. A. , Robust self concurrent test of linear digital systems, Proceedings 10th Asian Test Symposium, 2001.
DOI : 10.1109/ATS.2001.990298

URL : https://hal.archives-ouvertes.fr/hal-00015844

R. Singh and J. Knight, Concurrent testing in high level synthesis, Proceedings of 7th International Symposium on High-Level Synthesis, 1994.
DOI : 10.1109/ISHLS.1994.302335

D. J. Smith, Vhdl & verilog compared & contrasted -plus modeled example written in vhdl, 33rd Design Automation Conference, pp.771-776, 1996.

S. W. Smith, The Scientist and Engineer's Guide to Digital Signal Processing, 1999.

P. L. Soucek and T. I. Group, Dynamic, Genetic, and Chaotic Programming, 1992.

J. E. Steensma, Testability analysis in high level data path synthesis, Journal of Electronic Testing, vol.3, issue.1, pp.43-56, 1993.
DOI : 10.1007/BF00971939

A. K. Susskind, Testing by verifying walsh coeecients, IEEE Transactions on Computers, issue.2, pp.32198-201, 1983.

K. Thearling and J. Abraham, An easily computed functional level testability measure, Proceedings. 'Meeting the Tests of Time'., International Test Conference, pp.381-390, 1998.
DOI : 10.1109/TEST.1989.82322

M. Vahidi and A. Orailoo-glu, Testability metrics for synthesis of self-testable design and eeective t e s t plans, IEEE ETC, pp.170-175, 1995.

J. L. Van-meerbergen, P. E. Lippens, W. F. Verhaegh, A. Van-der, and . Werf, PHIDEO: High-level synthesis for high throughput applications, Journal of VLSI signal processing systems for signal, image and video technology, vol.7, issue.1-2, pp.89-104, 1995.
DOI : 10.1007/BF02406472

I. Verbauwhede and J. M. Rabaey, Synthesis for real time systems: Solutions and challenges, Journal of VLSI signal processing systems for signal, image and video technology, vol.33, issue.No. 12, pp.67-88, 1995.
DOI : 10.1007/BF02406471

H. E. Wang, High-level synthesis of scalable architectures for iir lters using ultichip modules, 30th Design Automation Conference, pp.336-342, 1993.

T. W. Williams and K. P. , Design for Testability???A Survey, Proceedings of the IEEE, vol.71, issue.1, pp.98-112, 1983.
DOI : 10.1016/B978-1-55558-075-9.50021-1

M. E. Wolf and M. S. Lam, A loop transformation theory and an algorithm to maximize parallelism, IEEE Transactions on Parallel and Distributed Systems, vol.2, issue.4, pp.452-471, 1991.
DOI : 10.1109/71.97902

W. Wolf, Redundancy removal during high-level synthesis using scheduling don't cares, Journal of Electronic Testing: Theory and Applications, issue.11, pp.211-225, 1997.

N. Wooand and J. Kim, An eecient method of partitioning circuits for multiple-fpga implementation, 30th Design Automation Conference, pp.202-207, 1993.

L. and Y. Long, Recent developments in high-level synthesis, ACM Transactions on Design Automation of Electronic Systems, vol.2, issue.1, pp.2-21, 1997.

A. Y. Zomaya and S. Olariu, Special Issue on Parallel Evolutionary Computing, Journal of Parallel and Distributed Computing, vol.47, issue.1, pp.1-7, 1997.
DOI : 10.1006/jpdc.1997.1391