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Synthèse de haut niveau pour la testabilité en-ligne

Abstract : The need of on-line testing techniques is getting more and more important. Despite the growing complexity of digital systems, the integration of such techniques in the design flow must guarantee a reasonable cost in time-to-market, implicated resource and performance of the final design. This implies the development of new high-level synthesis methods which must respect tow main constraints. The first one is to handle complex digital systems in a reasonable time and resource. The second one is to take in consideration the on-line test constraints early in the high-level synthesis. In response to this problem, the present study proposes tow main issues. First, tow on-line test methods, non-concurrent and semi-concurrent, are presented as integrated solutions (BIST). And second, a new high-level synthesis (HLS) method, which takes in consideration the on-line test constraints, is developed. The on-line test constraints are considered at the compilation of the behavioural specifications into a graph-based representation (DFG). Then one of the developed on-line test method is integrated to the design at the scheduling step. The choice of the on-line test method depends on the imposed constraints on the system. The input of the proposed method is a behavioural specifications of a digital system. At first, an on-line testability oriented optimisation is applied on the arithmetic equations in the system. In addition of enhancing the on-line testability of the system, this optimisation can result in better design performance. The optimised behavioural description is compiled in a scheduled data flow graph (DFG). The compilation and scheduling tasks are resolved by an adapted genetic algorithm (GA). The on-line test, area and timing constraints are addressed at this stage of synthesis to produce a satisfied solution. Once the scheduled DFG obtained, the adapted on-line test method is inserted in the nominal scheduling of the system. The resource allocation and binding generate then the on-line testable RTL structure of the system. Key words: high level synthesis, compilation, scheduling, on-line testability, DFG, BIST, GA.
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Submitted on : Tuesday, July 17, 2007 - 12:22:32 PM
Last modification on : Friday, December 11, 2020 - 8:28:04 AM
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  • HAL Id : tel-00163332, version 1




M.A. Naal. Synthèse de haut niveau pour la testabilité en-ligne. Micro et nanotechnologies/Microélectronique. Institut National Polytechnique de Grenoble - INPG, 2002. Français. ⟨tel-00163332⟩



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