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Contributions à l'Arithmétique des Ordinateurs : Vers une Maîtrise de la Précision

Abstract : Since the apparition of the first computer, floating point arithmetic have drastically changed. The IEEE standard of implementation has been successful in settling the specifications of modern computer arithmetic, but the scientists are loosing rapidly the control and the validation of their computations. In spite of the huge amount of work associated to the definition of the standard operations, the numerical validation of a program cannot always be left to the arithmetic implemented on the computer. I am presenting in the first part of these studies two extensions to offer to the user a higher chance of validity : a new rounding mode adapted to the elementary functions and an efficient coding for the intervals that could be used easily by end users. I present in the first part of my work a detailled definition of the unit in the last place function and the probability of absorption or propagation of round-off errors in a stream of multiplications. This work, added to the former work of many research groups and the proposal contained in my master thesis clearly show the benefits that could be drawn from the proposed extensions. It is possible with on-line arithmetic to adapt at each step the precision of computation, but the basic operators are not adapted to modern 32 bit or 64 bit architectures. An efficient implementation of on-line operators will necessarily involve a description of a low level circuit. The Field Programmable Gate Array, are electronic component in which each logic part can be configured. By using FPGAs, we are able to lower the cost of production of a new circuit since we do not need a prototype. We have implemented with these technologies the common on-line operators : addition, normalization and so on... The kernel for on-line arithmetic (in French, Nacel) defined in this dissertation has been used to implement more evolved arithmetic operators as the multiplication, the division, the extraction of square root and the elementary functions through a polynomial approximation. Data-flow architectures are not sensitive to the difficulties that arise in the design of modern computers : memory access, communication latency, partial use of the instruction pipeline. I shall describe in this work the functionnal model for a small on-line arithmetic virtual unit (in French, Puce). By implementing a token mechanism equivalent to the process implemented on the Manchester Data-Flow Machine, Puce is able to reproduce the behavior of a small data-flow machine. We have added to the model the basics for on-line arithmetic, and Puce is able to evaluate on-line any numerical expression. We shall present towards the end of this work the result of a software simulation of Puce on a Fast Fourier Transform to validate the model of evaluation.
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Contributor : Marc Daumas <>
Submitted on : Thursday, May 17, 2007 - 5:45:24 PM
Last modification on : Thursday, November 21, 2019 - 2:12:42 AM
Long-term archiving on: : Wednesday, April 7, 2010 - 2:23:16 AM


  • HAL Id : tel-00147426, version 1



Marc Daumas. Contributions à l'Arithmétique des Ordinateurs : Vers une Maîtrise de la Précision. Autre [cs.OH]. Ecole normale supérieure de lyon - ENS LYON, 1996. Français. ⟨tel-00147426⟩



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