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Mécanismes de transport, courants de fuite ultra-faibles et rétention dans les mémoires non volatiles à grille flottante

Abstract : The commercial market of non volatile floating gate memories is considerably growing due to their increasing use in all electronic applications domains and as a consequence in a great number of industrial sectors. Nevertheless a further integration of these memory devices is limited by the impossibility to reduce the thickness of the SiO$_2$ tunnel oxide layer isolating the floating gate which contains the charge information. In fact, under a critical thickness of 7~nm, leakage currents induced by cumulated programming cycles lead to floating gate charge losses which drastically reduce the retention time and the life time of memory cells. These leakage currents are commonly called Stress Induced Leakage Currents (SILC).

During this doctoral work, in order to obtain reliable measurements of SILC currents, we have optimized a very low level experimental set-up which allows to reach the resolution ($10^{-15}$ A) of most performant electrometers. We then implemented the so-called "floating gate technique" which leads to an indirect evaluation of ultra-low level (inferior to $10^{-16}$ A) leakage currents. From a great number of experimental measurements performed on 7 to 8 nm thick tunnel oxides from a FLOTOX-EEPROM technology, a new model of trap assisted tunneling conduction mechanism was developed. Thanks to a new methodology, the spatial and energetical distributions of defects in tunnel oxides were extracted. Moreover it was shown that their stable negative charging can account for the voltage shifts of Fowler-Nordheim injection laws, which are responsible for the programming window closure of memory cells. The proposed model leads finally to a good agreement between experimental and simulated current-voltage characteristics in all the electric field and degradation level domains.

In a last phase, the floating gate devices were modelized from a dynamic point of view. The influence of programming pulses parameters on the critical stressing electrical values was analyzed. Floating gate charge loss kinetic in retention conditions was explicited as a function of tunnel oxide leakage current. From measurements performed on floating gate test structures, retention times on elementary EEPROM cells were extrapolated as a function of degradation level.
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Contributor : Stéphane Burignat <>
Submitted on : Tuesday, April 24, 2007 - 6:49:08 PM
Last modification on : Wednesday, July 8, 2020 - 12:42:08 PM
Long-term archiving on: : Wednesday, April 7, 2010 - 12:07:03 AM


  • HAL Id : tel-00143276, version 1


Stéphane Burignat. Mécanismes de transport, courants de fuite ultra-faibles et rétention dans les mémoires non volatiles à grille flottante. Modélisation et simulation. INSA de Lyon, 2004. Français. ⟨tel-00143276⟩



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