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Ingénierie de grille pour application à la micro-électronique MOS sub-micronique

Abstract : For more than thirty years, microelectronics has been constantly evolving to match increasingly high demands for speed and complexity in integrated circuits (ICs). This has been made possible by device miniaturization, which is now reaching its physical limits with the materials used. Among the various problems and limitations associated with reduced channel length and oxide thickness (short channel effects, quantum effects, gate depletion, breakdown, quasi-breakdown, SILC ¿), we have been focusing first on the PMOS structure, and in particular on reducing boron penetration from the gate into the substrate, as it causes threshold voltage instabilities, and second, on improving ultra-thin gate oxide reliability, by diminishing dopant induced defects into the gate oxide. The first section is devoted to the technological state of the art through a bibliographic review. It appears interesting to use of an amorphous deposited gate and to introduce nitrogen at the gate/oxide interface to improve integrity of the ultra-thin silicon oxide. A technological alternative is presented relying on the development of a 200nm-thick amorphous gate based on in-situ nitrogen-doped silicon layer (called NIDOS) deposited by LPCVD (T<500°C) from disilane Si2H6 and ammonia NH3. The second section deals with the development of 200nm-thick NIDOS films, and their electrical and mechanical properties. It is shown that the gate should consist of a bi-layer structure (5nm-thick NIDOS and 195nm-thick silicon) to minimize total resistivity of the polysilicon gate. In the third section, boron implantation is considered and we look at diffusion processes, highlighting a major reduction in boron diffusion in NIDOS films. Then, a NIDOS film deposited on the gate oxide turns out to be an interesting solution to keep the SiO2 integrity, and to prevent boron penetration into the substrate. The reliability of a capacitive structure such as polySi(P+) / NIDOS (5nm) / SiO2 (4.5nm) / Si is researched in the fourth section. Flat-band voltage measurements show, on the one hand, the role of the NIDOS layer as a barrier to boron diffusion, and interesting results in terms of ultra-thin oxide reliability (Qbd=60 C/cm _ @ -0.1 C/cm _), and, on the other, major gate depletion effects (> 20 %). The latter item could be improved either by additional annealing by RTP, or by developing an in-situ boron doped silicon gate.
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  • HAL Id : tel-00142309, version 1

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Laurent Jalabert. Ingénierie de grille pour application à la micro-électronique MOS sub-micronique. Micro et nanotechnologies/Microélectronique. Université Paul Sabatier - Toulouse III, 2001. Français. ⟨tel-00142309⟩

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