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Mécanismes Matériels pour des Transferts
Processeur Mémoire Sécurisés dans les
Systèmes Embarqués

Abstract : Today's embedded systems are considered as non trusted hosts since the owner, or anyone else who
succeeds in getting access, is a potential adversary. The bus between the System on Chip (SoC) and the external
memory is one of the weakest points of such systems because external memories contain sensitive data (end
users private data, software code...) which are usually exchanged in clear form over the bus. Therefore an
adversary may probe this bus in order to read private data or to retrieve software code (data confidentiality
concern). Another possible attack relies on code injection (data integrity concern). Thus, hardware mechanisms
must be designed to ensure data confidentiality and integrity. The conventional way to reach such a goal is to
implement a dedicated hardware engine for each security service. Being secured, this approach prevents
parallelizability of the underlying computations.
In this thesis, after a study of existing techniques and engines guaranteeing data confidentiality and
integrity, two hardware mechanisms dedicated to the security of processor-memory transactions are proposed.
First, a Parallelized Encryption and Integrity Checking Engine (PE-ICE) has been designed to provide an
effective solution to ensure both security services to data. PE-ICE allows full parallelizations on processor read
and write operations while optimizing the hardware resources required. Then, a technique based on a tree
structure (PRV-Tree – PE-ICE protected Reference Values) with the same property of full parallelization, is
specified to decrease the on-chip memory overhead implied by security mechanisms.
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Contributor : Elisabeth Greverie <>
Submitted on : Tuesday, April 17, 2007 - 5:26:06 PM
Last modification on : Thursday, May 24, 2018 - 3:59:20 PM
Long-term archiving on: : Wednesday, April 7, 2010 - 3:21:12 AM


  • HAL Id : tel-00142209, version 1



Reouven Elbaz. Mécanismes Matériels pour des Transferts
Processeur Mémoire Sécurisés dans les
Systèmes Embarqués. domain_stic.inge. Université Montpellier II - Sciences et Techniques du Languedoc, 2006. Français. ⟨tel-00142209⟩



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