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Caractérisation de défauts latents dans les circuits intégrés soumis à des décharges électrostatiques

Nicolas Guitard 1
1 LAAS-ISGE - Équipe Intégration de Systèmes de Gestion de l'Énergie
LAAS - Laboratoire d'analyse et d'architecture des systèmes
Abstract : Electrical stresses, such as electrostatic discharges (ESD) and electric overstress (EOS), are at the origin of more than 50% of integrated circuits failures. Moreover, with the advent of wireless technologies and the development of "X-by-wire" systems for automotive and aircraft applications, robustness specifications have become more severe. Concurrently, both shrinking and increasing complexity of semiconductor technologies increase their susceptibility to EOS/ESD stresses and generation of latent defects is more likely to occur. Finally, the required reliability levels in the majority of the applications are extremely high. To meet these new requirements, latent defects detection become essential. Due to feature size shrinking, the quiescent current of microelectronics circuits is increasing. This current increase will make difficult or impossible to detect latent defects susceptible to degrade the reliability of microelectronics systems. In this thesis, we studied the impact of latent defects induced by CDM ESD stresses on the reliability of integrated circuits, and proposed a new methodology for their detection. This methodology, based on low frequency noise measurements, enables the detection of latent defects with a higher sensitivity compared to leakage current measurement. The methodology was validated for simple ESD protection structures but also for complex commercial circuits submitted to CDM discharges. Various laser stimulation techniques were carried out for the localization of the generated defects and the validation of the physical mechanisms involved in the noise increase.
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Contributor : Emilie Marchand <>
Submitted on : Monday, April 2, 2007 - 9:29:40 AM
Last modification on : Thursday, June 10, 2021 - 3:06:52 AM
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  • HAL Id : tel-00139542, version 1


Nicolas Guitard. Caractérisation de défauts latents dans les circuits intégrés soumis à des décharges électrostatiques. Micro et nanotechnologies/Microélectronique. Université Paul Sabatier - Toulouse III, 2006. Français. ⟨tel-00139542⟩



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