C. Vco-voltage and . Oscillator, Oscillateur contrôlé en tension, composant que doit réguler la PLL analogique (figure 1.2.b)

P. Acco, Why do we linearise charge pump PLL equations so early. NDES'01, 2001.

P. Acco, Étude de la boucle à verrouillage de phase par impulsions de charge, prise en compte des aspects hybrides, Thèse Laboratoire d'étude des systèmes informatiques et automatiques, 2003.

K. Astrom and B. Wittenmark, Computer Controlled Systems, Theory and design, 1997.

M. Cassia, P. Shah, and E. Bruun, Analytical model and behavioral simulation approach for a ???? fractional-N synthesizer employing a sample-hold element, IEEE Transactions on Circuits And Systems-II : Analog And Digital Signal Processing, p.50, 2003.
DOI : 10.1109/TCSII.2003.819138

A. Chemori and M. Alamir, Generation of multi steps limit cycles for rabbit using a low dimensional (scalar) nonlinear predictive control scheme, IEEERSJ international conference on Intelligent Robots and Systems, 2004.

A. Chemori and M. Alamir, Limit cycle generation for a class of non-linear systems with jumps using a low dimensional predictive control, International Journal of Control, vol.48, issue.15, pp.781206-1217, 2005.
DOI : 10.1016/S0167-6911(99)00064-X

C. Chung and C. Lee, A New DLL-Based Approach for All-Digital Multiphase Clock Generation, IEEE Journal of Solid-State Circuits, vol.39, issue.3, 2004.
DOI : 10.1109/JSSC.2003.822890

G. Cibiel, Contribution à l'analyse d'amplificateurs microondes à très faible bruit de phase. Application à la réalisation d'une source à très haute pureté spectrale en bande C, Thèse LAAS, CNRS, 2003.

D. Cordeau, Étude comportementale et conception d'oscillateurs intégrés polyphases accordables en fréquence en technologie Si et SiGe pour les radiocommunications, Thèse École Supérieure d'Ingénieurs de Poitiers, 2004.

J. Crawford, Frequency Synthesizer Design Handbook, 1994.

D. Dalt and N. , A Design-Oriented Study of the Nonlinear Dynamics of Digital Bang-Bang PLLs. IEEE Transactions on circuits and systems-I : regular papers, 2005.

H. De-bellescize, La réception synchrone. L'Onde Électrique, pp.230-240, 1932.

J. Doyle, F. Bruce, and A. Tannenbaum, Feedback Control Theory, 1992.

P. Dudek, S. Szczepanski, and J. Hatfield, A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line, IEEE Journal of Solid-State Circuits, vol.35, issue.2, 2000.
DOI : 10.1109/4.823449

E. Ferre-pikal, J. Camparo, L. Cutler, L. Maleki, W. Riley et al., Draft revision of IEEE STD 1139-1988 standard definitions of physical quantities for fundamental frequency and time metrology-random instabilities, IEEE Intrnational Frequency Control Symposium, pp.338-357, 1997.

F. Gardner, Phaselock techniques, 3 rd edition, 2005.

B. Goldberg, Digital techniques in frequency synthesis, 1998.

A. Hajimiri and T. Lee, A general theory of phase noise in electrical oscillators, IEEE Journal of Solid-State Circuits, vol.33, issue.2, pp.179-194, 1998.
DOI : 10.1109/4.658619

H. Hikawa, Direct digital frequency synthesizer with multi-stage linear interpolation, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 2004.
DOI : 10.1109/ISCAS.2004.1328983

M. Houdebine and S. Dedieu, Procédé et dispositif de génération d'un signal par boucle à verrouillage de fréquence fractionnaire, p.413596, 2006.

M. Houdebine, S. Dedieu, M. Alamir, and O. Sename, A NEW FRACTIONAL FREQUENCY SYNTHESIZER ARCHITECTURE WITH STABILITY AND ROBUSTNESS ANALYSIS, Proceedings of the IFAC World Congress, 2005.
DOI : 10.3182/20050703-6-CZ-1902.01187

M. Houdebine, S. Dedieu, and J. Lajoinie, Procédé d'élaboration d'un mot numérique représentatif d'un rapport non-entier entre les périodes respectives de deux signaux, et dispositif correspondant, pp.6-07416, 2006.

M. Houdebine, S. Dedieu, O. Sename, and M. Alamir, A sampled spur free fractional frequency synthesizer and its noise analysis, 2006 Proceedings of the 32nd European Solid-State Circuits Conference, 2006.
DOI : 10.1109/ESSCIR.2006.307538
URL : https://hal.archives-ouvertes.fr/hal-00086709

H. Jiang, C. He, D. Chen, R. , and G. , Optimal loop parameter design of charge pump PLLs for jitter transfer charachteristic optimization. The, 45th Midwest Symposium on Circuits and Systems, 2002.

L. Joet, S. Dedieu, E. André, and D. Saias, Method and device for generating a signal with a frequency equal to the product of a reference frequency and a real number, 2002.

J. Kalisz, R. Szplet, J. Pasierbinski, and A. Poniecki, Field Programmable Gate Array Based Time-To-Digital Converter with 200ps Resolution, IEEE Transaction on instrumentation and Measurement, vol.46, issue.1, 1997.

G. Kolumbán, B. Frigyik, and M. Kennedy, Accurate baseband model for sampling phase lock-loop, IEE colloquium on Theory and Practice, 1999.

V. Kroupa, Phase Lock Loops and Frequency Synthesis, 2003.
DOI : 10.1002/0470014105

D. Leeson, A simple model of feedback oscillator noise spectrum, Proc. letters of IEEE, 1966.
DOI : 10.1109/PROC.1966.4682

J. Maget, Varactor and Inductors for Integrated RF circuits in Standard MOS Technologies, 2002.

S. Meninger, Low Phase Noise, High Bandwidth Frequency Synthesis Techniques, 2005.

S. Meninger and M. Perrott, Bandwidth extension of low noise fractional-N synthesizers, RFIC) Symposium, 2005. Digest of Papers. 2005 IEEE Radio Frequency integrated Circuits, pp.211-214, 2005.
DOI : 10.1109/RFIC.2005.1489634

M. Parle and M. Kennedy, Comments on the effectiveness of the Szabo and Kolumban solution to false lock in sampling PLL frequency synthesizer, Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005., 2005.
DOI : 10.1109/ECCTD.2005.1523148

B. Razavi, A study of phase noise in CMOS oscillator, IEEE journal of solid state circuits, issue.3, p.31, 1996.

W. Sander, Digital Phase Discriminations Based on Frequency Sampling. United States Patent No US 6, pp.135-136, 2001.

S. Skogestad and I. Postlethwaite, Multivariable Feedback Control : analysis and design, 2005.

R. Staszewski and P. Balsara, Phase-Domain All-Digital Phase-Locked Loop. IEEE Transaction on circuits and systems -II : Express briefs, 2005.
DOI : 10.1109/tcsii.2004.842067

R. Staszewski and P. Balsara, All-Digital Frequency Synthesizer in Deep- Submicron CMOS, 2006.
DOI : 10.1002/0470041951

R. Staszewski, D. Leipold, C. Hung, and P. Balsara, TDC-based frequency synthesizer for wireless applications, 2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers, 2004.
DOI : 10.1109/RFIC.2004.1320575

R. Staszewski, J. Wallberg, C. Hung, G. Feygin, M. Entezari et al., LMS-based calibration of an RF digitally controlled oscillator for mobile phones, IEEE Transactions on Circuits and Systems II : Express BriefsIEEE, pp.225-229, 2006.
DOI : 10.1109/TCSII.2005.858750

R. Staszewski, J. Wallberg, S. Rezeq, C. Hung, O. Eliezer et al., All-digital PLL and transmitter for mobile phones, IEEE Journal of Solid-State Circuits, vol.40, issue.12, p.40, 2005.
DOI : 10.1109/JSSC.2005.857417

J. Stensby, Stability of false lock states in a class of phase-lock loops, Proceedings of the Thirty-Fourth Southeastern Symposium on System Theory (Cat. No.02EX540), pp.133-137, 2002.
DOI : 10.1109/SSST.2002.1027020

Z. Szabó and G. Kolumbán, How to avoid false lock in SPLL frequency synthesizers, IEEE Transactions on Instrumentation and Measurement, vol.52, issue.3, pp.927-931, 2003.
DOI : 10.1109/TIM.2003.814676

Y. Tang, M. Ismail, and S. Bibyk, A new fast-settling gearshift adaptative PLL to extend loop bandwidth enhancement in frequency synthesizers, IEEE International Symposium on Circuits And Systems-ISCAS, 2002.

H. Taub and D. Schilling, Principles of Communication Systems, 1971.

R. Tonietto, Wideband All Digital PLL for Direct Modulation, Thèse de l'université de Pavia (Italie), 2005.

R. Tonietto, E. Zuffti, R. Castello, and I. Bietti, A 3MHz Bandwidth Low Noise RF All Digital PLL with 12ps Resolution Time to Digital Converter, 2006 Proceedings of the 32nd European Solid-State Circuits Conference, 2006.
DOI : 10.1109/ESSCIR.2006.307553

M. Van-paemel, Analysis of a charge-pump PLL: a new model, IEEE Transactions on Communications, vol.42, issue.7, p.42, 1994.
DOI : 10.1109/26.297861

C. Vaucher, Architectures for RF Frequency Synthesizers, 2002.

B. Zhang, P. E. Allen, and J. M. Huard, A Fast Switching PLL Frequency Synthesizer With an On-Chip Passive Discrete-Time Loop Filter in 0.25-µm CMOS, IEEE Journal of Solid-State Circuits, vol.38, issue.6, 2003.