H. [. Adriahantenaina, A. G. Charlery, and C. A. Mortiez, Zeferino ? « SPIN : a scalable, packet switched, on-chip micro-network, Proc. Design, Automation and Test in Europe Conference and Exhibition, 2003.

M. [. Agarwal, S. Hrishikesh, and . Keckler, Burger ? « Clock rate vs. IPC : The end of the road for conventional microprocessors, Proc. 27th Annual International Symposium on Computer Architecture, pp.248-259, 2000.

P. [. Angiolini, S. Meloni, and L. Carta, Benini et L. Raffo ? « Contrasting a noc and a traditional interconnect fabric with layout awareness, Proc. Design, Automation and Test in Europe Conference and Exhibition, pp.124-129, 2006.

D. Andreasson, Kumar ? « On improving best-effort throughput by better utilization of guaranteed throughput channels in an on-chip communication system, Proc. 22nd IEEE Norchip Conference, pp.265-268, 2004.

I. [. Bolotin, R. Cidon, and . Ginosar, Kolodny ? « Cost considerations in network on chip », Integration -The VLSI Journal, pp.19-42, 2003.

«. [. Bibliographie and . Qnoc, QoS architecture and design process for network on chip, Journal of Systems Architecture, special issue on Network on Chip, vol.50, pp.105-128, 2004.

F. [. Beigne, P. Clermidy, and A. Vivet, Clouard et M. Renaudin ? « An asynchronous noc architecture providing low latency service and its multi-level design framework, Proc. 11th IEEE International Symposium on Asynchronous Circuits and Systems, pp.54-63, 2005.

J. Bainbridge, S. Furber, and ?. Chain, Chain: a delay-insensitive chip area interconnect, IEEE Micro, vol.22, issue.5, pp.16-23, 2002.
DOI : 10.1109/MM.2002.1044296

N. Banerjee and P. Vellanki, Chatha ? « A power and performance model for network-on-chip architectures, Proc. Design, Automation and Test in Europe Conference and Exhibition, pp.1250-1255, 2004.

]. L. Bemi01 and G. D. Benini, Micheli ? « Powering networks on chips, Proc. 14th International Symposium on Systems Synthesis, pp.33-38, 2001.

P. Bhojwani, Mahapatra ? « Interfacing cores with on-chip packetswitched networks, Proc. 16th International Conference on VLSI Design, pp.382-387, 2003.

]. T. Bjsp05 and . Bjerregaard, Sparso ? « A router architecture for connectionoriented service guarantees in the mango clockless network-on-chip, Proc. Design, Automation and Test in Europe, pp.1226-1231, 2005.

]. D. Blga01 and K. Blaauw, Gala ? « Deep-submicron issues in high-performance design, Proc. International Workshop on Power And Timing Modeling, Optimization and Simulation, 2001.

L. [. Chang, M. Cook, G. Hunt, and A. Martin, McNelly et L. Todd ? Surviving the SoC revolution : A guide to platform-based design, 1999.

F. [. Clouard, K. Ghenassia, L. Jain, and J. P. Maillet-contoz, Strassen ? « Using transaction-level models in a SoC design flow, SystemC : Methodologies and Applications (W. Muller, W. Rosenstiel et J. Ruf, pp.29-63, 2003.

]. P. Cobm02 and A. Coussy, Baganne et E. Martin ? « Analyse fonctionnelle des moyens de communication proposés dans les systèmes sur silicium, Proc. Journées Francophones sur l'Adéquation Algorithme Architecture, 2002.

]. D. Cusg99 and J. P. Culler, Singh et A. Gupta ? Parallel computer architecture : A hardware/software approach, 1999.

K. [. Radulescu and . Goossens, Rijpkema ? « Concepts and implementation of the philips network-on-chip, Proc. International Workshop on IP Based System-on-Chip Design, 2003.

]. W. Dato01, Dally et B. Towles ? « Route packets, not wires : on-chip interconnection networks, Proc. Design Automation Conference, pp.684-689, 2001.

]. W. Dall90, Dally ? « Virtual-channel flow control, Proc. 17th Annual International Symposium Computer Architecture, pp.60-68, 1990.

]. Y. Dubl05, C. Durand, D. Bernard, ?. Lattard, and . Faust, on-chip distributed architecture for a 4G baseband modem SoC, Proc. Design and Reuse IP-SOC, pp.51-55, 2005.

]. K. Faka03 and S. Fazel, Kaiser ? Multi-carrier and spread spectrum systems, 2003.

]. D. Flyn97, ?. Flynn, and . Amba, AMBA: enabling reusable on-chip designs, IEEE Micro, vol.17, issue.4, pp.20-27, 1997.
DOI : 10.1109/40.612211

S. [. Goossens, J. Gonzalez-pestana, O. P. Dielissen, J. Gangwal, A. Van-meerbergen et al., Wielage ? « Service-based design of systems on chip and networks on chip, Dynamic and Robust Streaming In And Between Connected Consumer-Electronics Devices (P. van der Stok Philips Research Book Series, pp.37-60, 2005.

P. [. Grecu and A. Pande, Ivanov et R. Saleh ? « Structured interconnect architecture : A solution for the non-scalability of bus-based socs, Proc. Great Lakes Symposium VLSI, pp.192-195, 2004.

]. C. Glni94 and . Glass, Ni ? « The turn model for adaptive routing, Journal of the Association for Computing Machinery, vol.41, pp.874-902, 1994.

]. P. Gugr00 and . Guerrier, Greiner ? « A generic architecture for on-chip packetswitched interconnections, Proc. Design, Automation and Test in Europe Conference and Exhibition, pp.250-256, 2000.

G. [. Hegedus and . Maggio, Kocarev ? « A ns-2 simulator utilizing chaotic maps for network-on-chip traffic analysis, Proc. IEEE International Symposium on Circuits and Systems, pp.3375-3378, 2005.

]. R. Hodr02 and . Hofmann, Drerup ? « Next generation CoreConnect? processor local bus architecture, Proc. 15th Annual IEEE International ASIC/SOC Conference, pp.221-225, 2002.

]. R. Hohk03 and M. Holsmark, Hogberg et S. Kumar ? « Modelling and evaluation of a network on chip architecture using sdl, Proc. 11th SDL Forum, 2003.

]. R. Homh01, K. Ho, and M. A. Mai, Horowitz ? « The future of wires, IEEE, vol.89, pp.490-504, 2001.

]. K. Holt05, ?. Holt, and L. Wireless, Past, present, and future, Proc. Design, Automation and Test in Europe, pp.92-93, 2005.

J. Hu and R. , Marculescu ? « Dyad -smart routing for networks-on-chip, Proc. 41st Design Automation Conference, pp.260-263, 2004.

H. ». Document-interne, C. Grenoble, and C. Grenoble, Spécification du bloc IT manager d'une unité HW », Document interne, Spécification du bloc Input d'une unité HW », Document interne,ITRS05] « International roadmap for semiconductorsitrs.net. [JVLZ05] M. Juntti, M. Vehkapera, J. Leinonen, V. Zexian, D. Tujkovic , S. Tsumura et S. Hara ? « MIMO MC-CDMA communications for future cellular systems, pp.118-124, 2003.

A. Jerraya and H. , Guest Editors' Introduction: Multiprocessor Systems-on-Chips, Computer, vol.38, issue.7, pp.36-40, 2005.
DOI : 10.1109/MC.2005.231

URL : https://hal.archives-ouvertes.fr/hal-00080314

M. [. Kogel, A. Doerper, R. Wieferink, G. Leupers, and H. Ascheid, Meyr et S. Goossens ? « A modular simulation framework for architectural exploration of on-chip interconnection networks, Proc. 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pp.7-12, 2003.

A. [. Kumar, J. Jantsch, M. Soininen, M. Forsell, J. Millberg et al., Tiensyrja et A. Hemani ? « A network on chip architecture and design methodology, Proc. IEEE Computer Society Annual Symposium on VLSI, pp.105-112, 2002.

F. Karim, A. Nguyen, and S. Dey, Rao ? « On-chip communication architecture for OC-768 network processors, Proc. Design Automation Conference, pp.678-683, 2001.

A. [. Keutzer, J. Newton, and . Rabaey, System-level design: orthogonalization of concerns and platform-based design, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.19, issue.12, pp.1523-1543, 2000.
DOI : 10.1109/43.898830

M. Karol and M. , Input Versus Output Queueing on a Space-Division Packet Switch, IEEE Transactions on Communications, vol.35, issue.12, pp.1347-1356, 1987.
DOI : 10.1109/TCOM.1987.1096719

F. Karim, A. Nguyen, and S. , An interconnect architecture for networking systems on chips, IEEE Micro, vol.22, issue.5, pp.36-45, 2002.
DOI : 10.1109/MM.2002.1044298

F. [. Lemaire, Y. Clermidy, D. Durand, and A. A. Lattard, Jerraya ? « Performance evaluation of a NoC-based design for MC-CDMA telecommunications using NS-2, Proc. 16th IEEE International Workshop on Rapid System Prototyping, 2005.

R. Lemaire, Y. Durand, D. Lattard, and A. A. , Jerraya ? « A semidistributed control system for application management in a NoC-based architecture, Proc. 24th IEEE Norchip Conference, 2006.

. [. Bibliographie, D. Lemaire, and F. Lattard, Clermidy et C. Bernard ? « Système sur puce à controle semi-distribué », Mars, Brevet Numéro E.N, pp.6-50892, 2006.

]. K. Lard01 and A. Lahiri, Raghunathan et S. Dey ? « Evaluation of the trafficperformance characteristics of system-on-chip communication architectures, Proc. 14th International Conference on VLSI Design, pp.29-35, 2001.

]. R. Lelj05, D. Lemaire, and A. A. Lattard, Jerraya ? « Évaluation des performances de transferts de données sur un noc régulé par un mécanisme de contrôle de flux, Proc. Journées Nationales du Réseau de Doctorants en Microélectronique, 2005.

]. J. List00, S. Liang, R. Swaminathan, and ?. Tessier, A scalable, singlechip communications architecture, Proc. IEEE International Conference on Parallel Architectures and Compilation Techniques, pp.37-46, 2000.

A. [. Marescaux, D. Bartic, S. Verkest, and . Vernalde, Lauwereins ? « Interconnection networks enable fine-grain dynamic multitasking on FPGAs, Proc. the reconfigurable computing is going mainstream , 12th International Conference on Field-Programmable Logic and Applications, pp.795-805, 2002.
DOI : 10.1007/3-540-46117-5_82

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.14.7398

A. [. Meincke, S. Hemani, P. Kumar, J. Ellervee, T. Oberg et al., Tenhunen ? « Globally asynchronous locally synchronous architecture for large high-performance ASICs, Proc. IEEE International Symposium on Circuits and Systems, pp.512-515, 1999.

J. [. Marescaux, A. Mignolet, W. Bartic, D. Moffat, and S. Verkest, Vernalde et R. Lauwereins ? « Networks on chip as hardware components of an OS for reconfigurable systems, Proc. 13th International Conference on Field Programmable Logic and Applications, 2003.

A. [. Moraes, L. Mello, and L. Möller, Ost et N. Calazans ? « Low area overhead packet-switched network on chip : Architecture and prototyping, Proc. IFIP International Conference on Very Large Scale Integration, 2003.

M. Millberg, E. Nilsson, and R. Thid, Jantsch ? « Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip, Proc. Design Automation and Test Europe Conference, 2004.

M. Millberg, E. Nilsson, R. Thid, S. Kumar, and A. A. , Jantsch ? « The Nostrum backbone-a communication protocol stack for Networks on Bibliographie 167

L. [. Mello and N. Tedesco, Calazans et F. Moraes ? « Virtual channels in networks on chip : implementation and evaluation on Hermes NoC », 18th annual symposium on integrated circuits and system, pp.178-183, 2005.

J. Muttersbach, T. Villiger, H. Kaeslin, and N. , Felber et W. Fichtner ? « Globally-asynchronous locally-synchronous architectures to simplify the design of on-chip systems, Proc. 12th IEEE International ASIC/SOC Conference, pp.317-321, 1999.

]. N. Murb06, K. Muralimanohar, and . Ramani, Balasubramonian ? « Power efficient resource scaling in partitioned architectures through dynamic heterogeneity, Proc. IEEE International Symposium on Performance Analysis of Systems and Software, Mars, pp.100-111, 2006.

T. [. Nollet, P. Marescaux, D. Avasare, and J. Verkest, Mignolet ? « Centralized run-time resource management in a network-onchip containing reconfigurable hardware tiles, Proc. Design, Automation and Test in Europe, pp.234-239, 2005.

M. [. Nilsson, J. Millberg, and . Oberg, Jantsch ? « Load distribution with the proximity congestion awareness in a network on chip, Proc. Design, Automation and Test in Europe Conference and Exhibition, pp.1126-1127, 2003.

]. Ngch05 and H. Ngo, Choi ? « On chip network : topology design and evaluation using NS2, Proc. 7th International Conference on Advanced Communication Technology, pp.1292-1295, 2005.

. [. Bernard, Varreau ? « Spécification du bloc Output Communication Controler d'une unité HW », Document interne, 2004.

C. [. Pande, M. Grecu, and A. Jones, Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures, IEEE Transactions on Computers, vol.54, issue.8, pp.1025-1040, 2005.
DOI : 10.1109/TC.2005.134

[. Toolkit, ? « Application of a multi-processor SoC platform to highspeed packet forwarding, Proc. Design, Automation and Test in Europe Conference and Exhibition, pp.58-63, 2004.

E. [. Pestana, A. Rijpkema, K. Radulescu, and O. P. Goossens, Gangwal ? « Cost-performance trade-offs in networks on chip : a simulation-based approach, Proc. Design, Automation and Test in Europe Conference and Exhibition, pp.764-769, 2004.

J. [. Radulescu, S. G. Dielissen, O. P. Pestana, E. Gangwal, and P. Rijpkema, An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.24, issue.1, pp.4-17, 2005.
DOI : 10.1109/TCAD.2004.839493

R. E. Rijpkema, K. Goossens, A. Radulescu, J. Dielissen, J. Van-meerbergen et al., Wielage et E. Waterlander ? « Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip, Proc. Design, Automation and Test in Europe Conference and Exhibition, pp.350-355, 2003.

]. A. Rago02, K. Radulescu, E. Bhattacharyya, J. Deprettere, and . Teich, Goossens ? « Communication services for networks on chip », Domain-specific Embedded Multiprocessors, Dekker, 2003.

E. Rijpkema and K. , Goossens et P. Wielage ? « A router architecture for networks on silicon, Proc. 2nd Workshop on Embedded Systems, pp.181-188, 2001.

]. A. Rosv97 and J. A. Rowson, Sangiovanni-Vincentelli ? « Interface-based design, Proc. Design Automation Conference, pp.178-183, 1997.

M. Sgroi, M. Sheets, A. Mihal, K. Keutzer, S. Malik et al., Sangiovanni-Vincentelli ? « Addressing the system-on-a-chip interconnect woes through communication-based design, Proc. Design Automation Conference, pp.667-672, 2001.

]. D. Stnu02 and J. Siguenza-tortosa, Nurmi ? « VHDL-based simulation environment for Proteo NoC, Proc. 7th IEEE High-Level Design Validation and Test Workshop, pp.1-6, 2002.

L. [. Sassatelli, S. Torres, M. Riso, and . Robert, Moraes ? « A mesh based Network on Chip characterization : A GALS approach, Proc. 20th International Conference on Design of Circuits and Integrated Systems, 2005.

]. Sukj02, S. Sun, and . Kumar, Jantsch ? « Simulation and evaluation for a network on chip architecture using ns, Proc. 20th IEEE Norchip Conference, 2002.

G. [. Theocharides and N. Link, Vijaykrishnan et M. Irwin ? « Implementing ldpc decoding on network-on-chip, Proc. 18th International Conference on VLSI Design, pp.134-137, 2005.

. Opencores, org ? « Wishbone, revision b.3 specification, 2002.

P. Wielage, Goossens ? « Networks on silicon : blessing or nightmare ?, Proc. Euromicro Symposium on Digital System Design, pp.196-200, 2002.
DOI : 10.1109/dsd.2002.1115369

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.18.6063

]. D. Wili03, D. Wiklund, and . Liu, ? « SoCBUS : switched network on chip for hard real time embedded systems, Proc. International Parallel and Distributed Processing Symposium, 2003.

D. Wiklund, S. Sathe, and D. , Liu ? « Network on chip simulations for benchmarking, Proc. 4th IEEE International Workshop on System-on- Chip for Real-Time Applications, pp.269-274, 2004.

W. [. Xu, J. Wolf, S. Henkel, and . Chakradhar, Lv ? « A case study in networks-on-chip design for embedded video, Proc. Design, Automation and Test in Europe Conference and Exhibition, pp.770-775, 2004.

]. T. Yebm03b, L. Ye, and . Benini, De Micheli ? « Packetization and routing analysis of on-chip multiprocessor networks, Journal of Systems Architecture, vol.50, pp.81-104, 2004.

]. G. Yelf93 and J. Yee, Linnartz ? « Multicarrier CDMA in indoor wireless radio networks, IEEE Personal Indoor and Mobile Radio Communications, pp.109-113, 1993.

M. [. Zeferino, L. Kreutz, and A. A. Carro, Susin ? « A study on communication issues for systems-on-chip, Proc. 15th Symposium on Integrated Circuits and Systems Design, 2002.

]. C. Zesu03 and A. A. Zeferino, Susin ? « SoCIN : a parametric and scalable network-on-chip, Proc. 16th Symposium on Integrated Circuits and Systems Design, pp.169-174, 2003.

S. Du, Graphe d'états du séquenceur d'instruction, p.127