R. A. Hapman, Trends in CMOS process integration, Electrochem. Soc

L. C. Parillo, VLSI process integration", VLSI Technology, pp.455-505, 1983.

T. Skotnicki, Transistor MOS et se technologie de fabrication, 2000.

F. M. Wanlass and C. T. Sah, Nanowatt logic using field-effect metal-oxidesemiconductor triodes, IEEE Solid State Circuits Conf, p.32, 1963.
DOI : 10.1142/9789814503464_0081

T. Ozhone, H. Shimura, K. Tsuji, and T. Hirao, Silicon-gate n -well CMOS process by full ion implantation technology, IEEE Transactions on Electron Devices

L. C. Parillo, R. S. Payne, R. E. Davis, G. W. Reutlinger, and R. L. Field, Twin-tub CMOS - A technology for VLSI circuits, 1980 International Electron Devices Meeting, p.752, 1980.
DOI : 10.1109/IEDM.1980.189946

N. , T. Yasui, and N. Tanimura, Advanced Hi-CMOS device technology, IEEE Int. Electron Devices Meet, p.534, 1981.

D. B. Scott, Y. C. See, C. K. Lau, and R. D. Davis, Considerations for scaled CMOS source/drains, 1981 International Electron Devices Meeting, p.539, 1981.
DOI : 10.1109/IEDM.1981.190139

J. N. Burghartz, BiCMOS-Proze???integration und Bauelementoptimierung: Gundlegende Konzepte und neue Trends, Electrical Engineering, vol.44, issue.5, pp.313-327, 1996.
DOI : 10.1007/BF01235872

L. C. Parillo, Process and device characterization for micron and submicron CMOS technology, Dig. IEDM, pp.398-402, 1985.

S. Ogura, C. F. Codella, N. Rovedo, J. F. Shepard, and J. Riseman, A halfmicron MOSFET using double-implanted LDD, Dig. IEDM, pp.718-721, 1982.

J. Chen, T. Y. Chan, I. C. Chen, P. K. Ko, and C. Hu, Subbreakdown drain leakage current in MOSFET, IEEE Electron Device Letters, vol.8, issue.11, pp.515-517, 1987.
DOI : 10.1109/EDL.1987.26713

J. Schultz and M. Bohr, A high performance 0,35 µm 3,3 V BiCMOS technology optimized for product porting from 0,6 µm 3,3 V BiCMOS technology, BCTM, pp.43-46, 1995.

. Mauer, A new planarization technique, using a combination of RIE and chemichal mechanichal polish (CMP), Dig. IEDM, pp.61-64, 1989.

J. Encinas, Circuits intégrés silicium bipolaires, 1991.

J. L. Regolini, Technologie de fabrication de la microélectronique. Filières technologiques, 1991.

E. F. Labuda and J. T. Clemens, Integrated circuit technology, Encyclopedia of chemichal technology, 1980.

J. De and P. , Transistors bipolaires intégrés, 1998.

H. C. Lin, J. C. Ho, R. R. Iyer, and K. Kwong, CMOS-bipolar transistor structure, IEEE Transactions on Electron. Devices, vol.6, pp.945-951, 1969.

R. H. Havemann and R. H. Eklund, Process integration issues for submicron BiCMOS technology, Journal Solid State Tech, vol.35, pp.71-76, 1992.

H. Yoshida, H. Suzuki, Y. Kinoshita, K. Imai, T. Akimoto et al., Process integration technology for low process complexity BiCMOS using trench collector sink, Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting, pp.230-233, 1994.
DOI : 10.1109/BIPOL.1994.587901

T. , D. Sutherland, G. Jolly, and I. Emesh, A sub-micron BiCMOS technology for telecommunications, Microel. Eng, vol.15, pp.513-516, 1991.

R. Haddaway, T. Brown, K. Harris, and R. Foucault, BiCMOS technology for telecommunications, Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting BIPOL-93, pp.159-166, 1993.
DOI : 10.1109/BIPOL.1993.617489

P. G. Tsui, P. V. Gilbert, and S. W. Sun, A versatile half-micron complementary BiCMOS technology for microprocessor-based smart power applications, IEEE Transactions on Electron Devices, vol.42, issue.3, pp.42-564, 1995.
DOI : 10.1109/16.368055

A. Andrei, C. Contiero, and P. Galbiati, Multipower BCD 250 V : A versatile technology to realize high performance PICs, Proc. ESSDERC, pp.33-36, 1987.

J. S. Witters, A modular BICMOS technology including 85V DMOS devices for analogue/digital ASIC applications, Microelectronic Engineering, vol.19, issue.1-4, pp.555-560, 1992.
DOI : 10.1016/0167-9317(92)90495-D

S. , M. M. Gilbert, G. D. Berg, S. Wu, M. Soyuer et al., A 200 mm SiGe-HBT BiCMOS technology for mixed signal applications, Proc. BCTM, pp.43-46, 1995.

T. Ikeda, T. Nakashima, S. Kubo, H. Jouba, and M. Yamawaki, A high performance CBiCMOS with novel self-aligned vertical PNP transistors, Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting, pp.238-241, 1994.
DOI : 10.1109/BIPOL.1994.587903

K. Higashitani, H. Honda, K. Ueda, M. Hatanaka, and S. Nagao, A novel CBiCMOS technology by DIIP process, Dig. Symp. VLSI Tech, pp.77-78, 1990.

S. Parke, F. Assaderaghi, J. Chen, J. King, C. Hu et al., A versatile SOI BiCMOS technology with complementary lateral BJTs, IEDM, pp.453-456, 1992.

D. Ueda, H. Takagi, and G. Kano, A new vertical power MOSFET structure with extremely reduced on-resistance, IEEE Transactions on Electron Devices, vol.32, issue.1, pp.1-2, 1984.
DOI : 10.1109/T-ED.1985.21900

D. M. Brown and B. A. Heath, Reactive Ion Beam E tching of SiO 2 and polycristalline silicon, Journal of Applied Physics Letters, vol.37, pp.15-159, 1980.

V. Rumennik, Power device are in the chip, IEEE Spectrum, pp.42-48, 1985.

R. Pezzani and J. B. Quoirin, Functional integration of power devices : A new approach, European Power Elctronics (EPE'95), pp.2219-2223, 1995.

R. Pezzani, E. Bernier, and C. Ballon, A methodology for the functionnal power integration. Example, the evolution of the solid state protection in the TELECOM area, European Power Electronics (EPE'97), pp.1296-1301, 1997.

J. L. Sanchez, P. Austin, R. Berriane, and M. Marmouget, Trends in design and technology for new power integrated devices based on fuctional integration, European Power Electronic (EPE'97), pp.1302-1307, 1997.

R. Pezzani, Monolithic semiconductor switch and supply circuit component, 1996.

R. Pezzani, Three-state monolithic static switch, 1997.

R. Pezzani and E. Bernier, Programmable protection circuit and its monolithic manufacturing, Patent Number : RE, vol.35, p.854, 1995.

R. Pezzani, Thyristor control switch for a bidirectional motor, p.5

B. J. Baliga, Enha ncement -and depletion -mode vertical -channel MOS gated thyristors, Electronics Letters, vol.15, p.20, 1979.

A. Jaecklin, A N FET-Drivin power thyristor, IEEE Transactions on Electron. Devices, pp.34-39, 1987.

D. Darees, Contribution à l'étude d'associations monolithiques de composants MOS et bipolaires : le thyristor à gachette isolée, 1986.

J. Sanchez and P. Leturcq, Thyristor à gachette isolée planar haute tension (1400 volts) : un exemple d'interrupteur intégré de puissance, Electronique de Puissance du Futur (EPF'90), 1990.

B. Baliga, The MOS-gated emitter switched thyristor, Proceedings of the 2nd International Symposium on Power Semiconductor Devices and Ics. ISPSD '90., pp.75-77, 1990.
DOI : 10.1109/ISPSD.1990.991070

K. Lilja and T. Stockmeier, The FiBs, a new high voltage BiMOS switch, Proceedings of the 4th International Symposium on Power Semiconductor Devices and Ics, pp.261-265, 1992.
DOI : 10.1109/ISPSD.1992.991283

M. Mino, T. Yachi, A. Tago, K. Yanagisawa, and K. Sakakibara, A new planar microtransformer for use in micro-switching converters, IEEE Transactions on Magnetics, vol.28, issue.4, 1992.
DOI : 10.1109/20.144755

S. Sugahhara, M. Edo, T. Sato, and K. Yamasawa, The optimum chip size of a thin film reactor for a high-efficiency operation of a micro DC-DC converter, Proceeding of the Power Electronic Specialists Conference (PESC'98), pp.1499-1503

C. R. Sullivan and S. R. Sanders, Measured performance of a high-power-density microfabricated transformer in a DC-DC converter, PESC Record. 27th Annual IEEE Power Electronics Specialists Conference, pp.1499-1503
DOI : 10.1109/PESC.1996.548594

H. Hakim, Intégration de composants passifs sur silicium, Thèse de doctorat de l'Institut National des Sciences Appliquées, 2001.

H. Hakim, J. P. Laur, J. L. Sanchez, E. Scheid, and P. Dubreuil, Nonlinear capacitors integration, 2000 International Semiconductor Conference. 23rd Edition. CAS 2000 Proceedings (Cat. No.00TH8486), 2001.
DOI : 10.1109/SMICND.2000.890240

M. Breil, Etude d'associations MOS-Thyristor autoamorçables et blocables Exemple d'intégration de la fonction thyristor dual, Thèse de doctorat de l'Institut National des Sciences Appliquées, 1998.

M. R. Mac and . Pherson, The adjustment of MOS transistor threshold voltage by ion implantation, Applied Physics Letters, vol.18, issue.11, pp.502-504, 1971.

L. Forbes, n-channel ion-implanted enhancement/depletion FET circuit and fabrication technology, IEEE Journal of Solid-State Circuits, vol.8, issue.3, pp.226-230, 1973.
DOI : 10.1109/JSSC.1973.1050379

R. B. Fair, History of some early developments in ion-implantation technology leading to silicon transistor manufacturing, Proceedings of the IEEE, pp.111-137, 1998.
DOI : 10.1109/5.658764

R. Berriane, Conception et réalisation d'un thyristor à gâchette isolée commandé par voie optique : un exemple d'interrupteur intégré de puissance, Thèse de doctorat de l, 1993.

J. Arnould and P. Merle, Dispositifs de l'électronique de puissance, Traité des nouvelles Technologies Electroniques

O. Causse, Contribution à l'amélioration de la fonctionnalité et des performances de l'IGBT, Thèse de doctorat de l, 2001.

E. Scheid, L. Furgal, and H. Vergnes, Boron doped polysilicon deposition in a sector reactor : Specific phenomena and properties, Proceedings of EUROCVD 12
DOI : 10.1051/jp4:19998111

M. Marmouget, Contribution au développement d'outils d'aide à la conception de dispositifs de puissance basés sur le mode d'intégration fonctionnelle, Thèse de doctorat de l'Institut National des Sciences Appliquées, 2000.

S. Rael, C. Schaeffer, and J. P. Ferrieux, Etude de la mise en parallèle d'IGBT, Electronique de Puissance du Futur (EPF'92), 1992.

O. Causse, Contribution à l'amélioration de la fonctionnalité et des performances de l'IGBT, Thèse de doctorat de l'Université Paul-Sabatier, 2001.

Y. Cheron, La commutation douce dans la conversion statique de l'énergie électrique, Thèse de doctorat de l'Institut National Polytechnique, 1988.

]. L. Parillo, R. S. Payne, R. E. Davis, G. W. Reutlinger, and R. L. Field, Twin-tub CMOS - A technology for VLSI circuits, 1980 International Electron Devices Meeting, p.752, 1980.
DOI : 10.1109/IEDM.1980.189946

D. B. Scott, Y. C. See, C. K. Lau, and R. D. Davis, Considerations for scaled CMOS source/drains, 1981 International Electron Devices Meeting, p.539, 1981.
DOI : 10.1109/IEDM.1981.190139

R. S. Payne, W. N. Grant, and W. J. Bertram, Elimination of latch up in bulk CMOS, 1980 International Electron Devices Meeting, p.248, 1980.
DOI : 10.1109/IEDM.1980.189806

P. Anode and . Tout, abord, on protège la face avant, puis on réalise une gravure de l'oxyde de champ sur la face arrière (masque n°2) La réalisation de cette anode se fait ensuite par implantation ionique de bore sur la face arrière avec une énergie de 100 keV et une dose de 1, pp.16-18