, Hardware-software cosynthesis for microcontrollers, IEEE Design & Test of Computers, vol.10, issue.4, pp.64-75, 1993.
DOI : 10.1109/54.245964
, Hardware-Software Cosynthesis for Digital Systems, IEEE Journal Design and Test of Computers, pp.29-41, 1993.
, Specification and Design of Embedded System, IEEE Design & Test of Computers, pp.53-67, 1995.
, The interplay of run-time estimation and granularity in HW/SW partitioning, Proceedings of 4th International Workshop on Hardware/Software Co-Design. Codes/CASHE '96, 1996.
DOI : 10.1109/HCS.1996.492226
, A hardware/software partitioner using a dynamically determined granularity, Proceedings of the 34th annual conference on Design automation conference , DAC '97, pp.691-696, 1997.
DOI : 10.1145/266021.266323
, System-level synthesis using re-programmable components, [1992] Proceedings The European Conference on Design Automation, pp.2-7, 1992.
DOI : 10.1109/EDAC.1992.205881
, A Method for Partitioning UNITY Language in Hardware and Software, Proc. European Design Automation Conference (EuroDAC), pp.580-585, 1994.
, Hardware/Software Partitioning and Minimizing Memory Interface Traffic, of The European Conference on Design Automation (EuroDAC) 1994, pp.220-225, 1994.
, Processor reconfiguration through instruction-set metamorphosis, Computer, vol.26, issue.3, pp.11-18, 1993.
DOI : 10.1109/2.204677
, An Algorithm for Partitioning of Application Specific Systems, Proc. European Design & Test Conference, pp.316-321, 1993.
, Handouts from Eurochip course on Hardware, pp.14-18, 1995.
, An automatic hardware-software partitioner based on the possibilistic programming, Proceedings ED&TC European Design and Test Conference, pp.467-472, 1996.
DOI : 10.1109/EDTC.1996.494342
, A Binary?Constraint Search Algorithm for Minimizing Hardware during Hardware/Software Partitioning, of The European Conference on Design Automation (EuroDAC) 1994, pp.214-219, 1994.
, Clustering for improved system?level functional partitioning, Proc. of 8th. International Symposium on System Synthesis, pp.28-33, 1995.
, Multiple?Process Behavioural Synthesis for Mixed Hardware?Software Systems, IEEE/ACM Proc. of 8th. International Symposium on System Synthesis, pp.4-9, 1995.
, Thomas Multiple?Process Behavioural Synthesis for Mixed Hardware?Software Systems, 8th. International Symposium on System Synthesis, pp.10-15, 1995.
DOI : 10.1109/isss.1995.520606
, A global criticality/local phase driven algorithm for the constrained hardware/software partitioning problem, Third International Workshop on Hardware/Software Codesign, pp.42-48, 1994.
DOI : 10.1109/HSC.1994.336724
, Modifying min-cut for hardware and software functional partitioning, Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97, 1997.
DOI : 10.1109/HSC.1997.584577
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.56.7801
, An evolutionary approach to system-level synthesis, Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97, 1997.
DOI : 10.1109/HSC.1997.584597
, Design space exploration algorithm for heterogeneous multi-processor embedded system design, Proceedings of the 35th annual conference on Design automation conference , DAC '98, 1998.
DOI : 10.1145/277044.277060
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.32.1528
, Hardware-software co-design of embedded reconfigurable architectures, Proceedings of the 37th conference on Design automation , DAC '00, 2000.
DOI : 10.1145/337292.337559
, Kernel Scheduling in reconfigurable scheduling, 1999.
DOI : 10.1109/date.1999.761102
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.21.8193
, An automated temporal partitioning and loop fission approach for FPGA based reconfigurable synthesis of DSP applications, Design Automation Conference, 1999.
, The extended partitioning problem: hardware/software mapping and implementation bin selection, 6th International Workshop on Rapid Systems Prototyping, 1995.
, Sensitivity-driven cosynthesis of distributed embedded systems, Internation Symposium on System Synthesis, 1995.
, SOREL Optimized rapid prototyping for real time embedded heterogeneous multiprocessors, CODES'99 7th International Workshop on Hardware/ Software Co-Design, 1999.
, Critical path driven cosynthesis for heterogeneous target architecures
DOI : 10.1109/hsc.1997.584573
URL : http://orbit.dtu.dk/ws/files/4284756/Bj%C3%B8rn-J%C3%B8rgensen.pdf
, COSYN, Proceedings of the 34th annual conference on Design automation conference , DAC '97, 1997.
DOI : 10.1145/266021.266341
, A hardware/software co-synthesis technique based on heterogeneous multiprocessor scheduling, Codes'99, 1999.
, A Model and Methodology for Hardware-Software Codesign, Handouts of Int'l Wshp on Hardware-Software Co-design, 1993.
, A model and methodology for hardware-software codesign, IEEE Design & Test of Computers, vol.10, issue.3, pp.6-15, 1993.
DOI : 10.1109/54.232468
, A method for hardware software partitioning, CompEuro 1992 Proceedings Computer Systems and Software Engineering, 1992.
DOI : 10.1109/CMPEUR.1992.218469
, Rapid-prototyping of hardware and software in a unified framework, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers, pp.152-155, 1991.
DOI : 10.1109/ICCAD.1991.185217
, RAPID : A Tool for Hardware/Software Tradeoff Analysis, Proc. IFIP Conf. Hardware Description Languages (CHDL), Publ, 1993.
, Synthesis of application-specific multiprocessor architectures, Proceedings of the 28th conference on ACM/IEEE design automation conference , DAC '91, pp.8-13, 1991.
DOI : 10.1145/127601.127612
, COSYN, Proceedings of the 34th annual conference on Design automation conference , DAC '97, 1997.
DOI : 10.1145/266021.266341
, CODEF: a system level exploration tool, ICASSP, pp.7-11, 2001.
, Découpage Transformationnel pour la conception de systèmes Mixtes Logiciel, Thèse de doctorat, p.189, 1998.
, SOLAR: An Intermediate Format for System-Level Modeling and Synthesis, Codesign: Computer-Aided Software/Hardware Engineering, pp.145-175, 1995.
, A Formal Specification Model for Hardware/Software Codesign, 1993.
, Discrete-Event Systems, 1993.
DOI : 10.1007/0-8176-4404-0_4
, Modeling Concurrent Real-Time Processes using Discrete Events, 1998.
, Petri Net Theory and the Modeling of Systems, 1981.
, Modeling of Complex Systems Using Hierarchical Petri Nets, " in Codesign: Computer-Aided Software/Hardware Engineering, pp.128-144, 1995.
, A Petri Net Based Unified Representation for Hardware/Software Co- Design, 1995.
, A Comparison of Synchronous and Cyclo- Static Dataflow, Proc. 29th Asilomar Conference on Signals, Systems and Computers, pp.204-210, 1995.
, Communicating Sequential Processes, 1985.
, The ESTEREL language, Proc. IEEE, pp.1293-1304, 1991.
DOI : 10.1109/5.97299
URL : https://hal.archives-ouvertes.fr/inria-00075075
, Partitioning conditional data flow graphs for embedded system design, Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors, p.337, 2000.
DOI : 10.1109/ASAP.2000.862404
, Program implementation schemes for hardware-software systems, Wshp Handouts of Int'l Wshp on Hardware-Software Co-Design, 1992.
DOI : 10.1109/2.248880
URL : http://akebono.stanford.edu/users/cad/papers/coelho/computer94.ps.Z
, Program implementation schemes for hardware-software systems, Computer, vol.27, issue.1, pp.48-55, 1994.
DOI : 10.1109/2.248880
URL : http://akebono.stanford.edu/users/cad/papers/coelho/computer94.ps.Z
, A system-design methodology: executable-specification refinement, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC, pp.458-463, 1994.
DOI : 10.1109/EDTC.1994.326836
, Software Estimation from Executable Specifications, Proc. European Design Automation Conf. (EuroDAC), pp.47-57, 1994.
, A hardware-software codesign methodology for DSP applications, IEEE Design & Test of Computers, vol.10, issue.3, pp.16-28, 1993.
DOI : 10.1109/54.232469
, Manifestations of Heterogeneity in Hardware/Software Codesign, Proc. 31 st Design Automation Coference (DAC), pp.437-438, 1994.
, Rapid-prototyping of hardware and software in a unified framework, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers, 1992.
DOI : 10.1109/ICCAD.1991.185217
, Using VHDL for high-level, mixed-mode system simulation, IEEE Design & Test of Computers, vol.9, issue.3, pp.31-40, 1993.
DOI : 10.1109/54.156156
, A Formal Specification Model for Hardware/Software Codesign, Wshp Handouts of Int'l Wshp on Hardware-Software Co-Design, p.53, 1993.
, A High-Level Language and Silicon Compiler for Digital Signal Processing, Proc. IEEE CICC, Portlant, pp.213-216, 1985.
, DSP Design Tool Requirements for Embedded Systems: A Telecommunication Industrial Perspective, " in journal of VLSI Signal Processing (special issue on synthesis for real-time DSP), 1994.
, CODES: A practical Concurrent design Environment, Int'l Wshp on Hardware/Software Co-Design, 1992.
, HW/SW Co-Design With PRAMs Using CODES, Proc. IFIP Conf. Hardware Description Languages (CHDL), Publ, 1993.
DOI : 10.1016/B978-0-444-81641-2.50010-1
, A prototyping Environment for Control-Oriented HW/SW Systems using State-Charts, Activity-Charts and FPGA's, Proc. Euro-DAC with Euro-VHDL, pp.60-65, 1994.
, A Software-Hardware Co-Synthesis Approach to Digital System Simulation, IEEE Micro, pp.48-58, 1994.
, A development environment for the cosynthesis of embedded software/hardware systems, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC, pp.469-473, 1994.
DOI : 10.1109/EDTC.1994.326834
, Synthesis steps and design models for codesign, Computer, vol.28, issue.2, pp.44-52, 1995.
DOI : 10.1109/2.347999
URL : https://hal.archives-ouvertes.fr/hal-00008146
, The Chinook Hardware/Software Co-Synthesis System, Proc. International Symposium on System Synthesis, pp.22-27, 1995.
, Optimization by Simulated Annealing, Science, vol.220, issue.4598, pp.671-680, 1983.
DOI : 10.1126/science.220.4598.671
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.123.7607
, Genetic Algorithms in Search, Optimization,and Machine Learning, 1989.
, Méthodologie de Partitionnement Logiciel/Matériel pour Plateformes Reconfigurables Dynamiquement, 2004.
, A user' s guide to tabu search, Annals of Operations Research, vol.41, pp.3-28, 1993.
, Vulcan: a System for High-Level Partitioning of Synchronous Digital Circuits, 1991.
, Pace: A dynamic programming algorithm for hardware/software partitioning, Proceedings of 4th International Workshop on Hardware/Software Codesign, Codes/CASHE'96, pp.85-92, 1996.
, Optimal hardware/software partitioning for concurrent specification using dynamic programming, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design, 2000.
DOI : 10.1109/ICVD.2000.812593
, Optimal temporal partitioning and synthesis for reconfigurable architectures, Proceedings Design, Automation and Test in Europe, 1998.
DOI : 10.1109/DATE.1998.655887
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.40.4413
, An integrated partitioning and synthesis system for dynamically reconfigurable Multi-FPGA architectures, Reconfigurable Architectures Workshop (RAW'98), pp.31-36, 1998.
DOI : 10.1007/3-540-64359-1_669
, Algorithms for the partitioning of applications containing variable duration tasks on reconfigurable architectures, ACS/IEEE International Conference on Computer Systems and Applications, 2003. Book of Abstracts., pp.14-18, 2003.
DOI : 10.1109/AICCSA.2003.1227450
, Ishfaq Ahmad: Evaluation of a Semi-Static Approach to Mapping Dynamic Iterative Tasks onto Heterogeneous Computing Systems, pp.204-209
, Etude du partitionnement logiciel/materiel d'applications à distribution variable de charge de calcul, 2002.
, Arif Ghafoor: A semi-static approach to mapping dynamic iterative tasks onto heterogeneous computing systems, Journal of Parallel and Distributed Computing, vol.66, issue.1, 2006.
, Etude du partitionnement logiciel/matériel d'applications à distribution variable de charge de calcul, pp.334-338, 2002.
, List scheduling of parallel tasks, Information Processing Letters, vol.37, issue.5, pp.291-297, 1991.
DOI : 10.1016/0020-0190(91)90222-4
, Dynamic remapping of parallel computations with varying resource demands, IEEE Transactions on Computers, vol.37, issue.9, pp.1073-1087, 1988.
DOI : 10.1109/12.2258
, Energy advantages of microprocessor platforms with on-chip configurable logic, IEEE Design & Test of Computers, vol.19, issue.6, pp.36-43, 2002.
DOI : 10.1109/MDT.2002.1047742
, A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms, Design, Automation and Test in Europe, pp.396-397
DOI : 10.1109/DATE.2005.9
URL : https://hal.archives-ouvertes.fr/hal-00181546
, A configurable logic architecture for dynamic hardware/software partitioning, Proceedings Design, Automation and Test in Europe Conference and Exhibition, pp.480-485
DOI : 10.1109/DATE.2004.1268892
, Online hardware/software partitioning in networked embedded systems, ASP-DAC, vol.2005, pp.982-985
, Dynamic hardware-software partitioning on reconfigurable system-on-chip, The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings., pp.102-105
DOI : 10.1109/IWSOC.2003.1213015
, Exploration de l'espace de conception de SOC, de l'asservissement à la cooperation, 2005.
URL : https://hal.archives-ouvertes.fr/tel-00105917
, Architecture synchronisée par les données pour système reconfigurable, 2002.
, Tissu numérique cellulaire à routage et configuration dynamique, 2005.
, Architectures and Algorithms for Field Programmable Gate Arrays with Embedded Memory, Canada, 1997.
, MicroBlaze Hardware Reference Guide, 2001.
, Nios Soft Core Embedded Processor, 2000.
, Enabling hardwaresoftware multitasking on a reconfigurable computing platform for networked portable multimedia appliances, Proceedings of the International Conference on Engineering Reconfigurable Systems and Architecture (ERSA'02), pp.116-122, 2002.
, La rémanence des architectures reconfigurables : un critère significatif de classification des architectures, Proceedings of the JFAAA, pp.49-52, 2002.
, Remote and partial reconfiguration of FPGAs: tools and trends, Proceedings International Parallel and Distributed Processing Symposium, pp.177-185, 2003.
DOI : 10.1109/IPDPS.2003.1213326
, Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices, Proc. of the 13th International Conference on Field Programmable Logic and Applications (FPL'03), volume 2778 de LNCS, pp.575-584, 2003.
DOI : 10.1007/978-3-540-45234-8_56
, A time-multiplexed FPGA, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186), pp.22-28, 1997.
DOI : 10.1109/FPGA.1997.624601
, Partitionning and CoDesign Tolls & Methodology for Reconfigurable Computing : the EPICURE Philosophy, Proceeding of the Third International Workshop on Systems, 2003.
, Architecture reconfigurable méthodologie et modélisation VHDL pour la mise au point d'applications, 6ème Symposium en Architectures Nouvelles de Machines, SympA'6, pp.19-22, 2000.
, A dynamically reconfigurable logic engine with a multi-context/multi-mode unified-cell architecture, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278), 1999.
DOI : 10.1109/ISSCC.1999.759297
, Garp: a MIPS processor with a reconfigurable coprocessor, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186), pp.12-21, 1997.
DOI : 10.1109/FPGA.1997.624600
, MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications, IEEE Transactions on Computers, vol.49, issue.5, pp.465-481, 2000.
DOI : 10.1109/12.859540
, Upgraded DSP Core Tackles Future Communication Needs, Electonic design, pp.66-68, 2000.
, DSP processors hit the mainstream, Computer, vol.31, issue.8, pp.51-59, 1998.
DOI : 10.1109/2.707617
, MorphoSys, Proceedings of the 37th conference on Design automation , DAC '00, pp.465-481, 2000.
DOI : 10.1145/337292.337583
, Architectures Reconfigurables Dynamiquement pour les Systèmes sur Puce, 2002.
, Highly scalable dynamically reconfigurable systolic ring-architecture for DSP applications, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition, pp.553-557, 2002.
DOI : 10.1109/DATE.2002.998355
, Adaptative System on a Chip (aSoc) for Low-Power Signal Processing, Thirty-Fith Asilomar Conference on Signals, and Computers, 2001.
, Dynamically parameterized algorithms and architectures to exploit signal variations for improved performance and reduced power, 2001 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.01CH37221), 2001.
DOI : 10.1109/ICASSP.2001.941061
, Dynamically parameterized architectures for power-aware video coding: motion estimation and DCT, Proceedings Second International Workshop on Digital and Computational Video, 2001.
DOI : 10.1109/DCV.2001.929936
, An Architecture for Saclable On-Chip Communication, 2002.
, Architecture reconfigurable dynamiquement pour applications mobiles, 2003.
, Méthodologies d'évaluation et de prototypage des systèmes numériques integers, 1998.
, Augmenting a microprocessor with reconfigurable Hardware, 2000.
, The NAPA Adaptative Processing Architecture, IEEE Symposium on Field Programmable custom Computing Machines, pp.28-37, 1998.
, Infrastructure for design and management of relocatable tasks in a heterogeneous reconfigurable system-on-chip, 2003 Design, Automation and Test in Europe Conference and Exhibition, pp.986-991, 2003.
DOI : 10.1109/DATE.2003.1253733
, A configurable logic architecture for dynamic hardware/software partitioning, Proceedings Design, Automation and Test in Europe Conference and Exhibition, pp.480-485
DOI : 10.1109/DATE.2004.1268892
, CASPER: Concurrent hardware-software co-synthesis of hard real-time aperiodic and periodic specifications of embedded system architectures, Proceedings Design, Automation and Test in Europe, pp.118-124, 1998.
DOI : 10.1109/DATE.1998.655845
, une infrastructure de simulation modulaire pour l'évaluation de performances de systèmes temps réel, 2003.
, Interconnection Networks Enable Fine-Grain Dynamic Multi-Tasking on FPGA's " , FPL'02, pp.795-805
DOI : 10.1007/3-540-46117-5_82
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.14.7398
, A methodology for task based partitioning and scheduling of dynamically reconfigurable systems, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251), pp.324-325, 1998.
DOI : 10.1109/FPGA.1998.707937
, Research Issues in Operating Systems for Reconfigurable Computing, Proc. Of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'02), pp.10-16, 2002.
, Measuring Execution Time and Real-Time Performance, Embedded Systems Conference (ESC), 2001.
, CoDeNios, Proceedings of the 2002 workshop on Computer architecture education Held in conjunction with the 29th International Symposium on Computer Architecture, WCAE '02, pp.73-78, 2002.
DOI : 10.1145/1275462.1275480
, Static dependent costs for estimating execution time, Proc. of the 1994 ACM Conference on LISP and functional programming, pp.65-78, 1994.
, « Incremental Hardware Estimation During Hardware/Software Functional Partitioning » IEEE Transactions on very large scale integration (VLSI) Systems, pp.459-464, 1995.
DOI : 10.1109/92.407006
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.49.9369
, Dynamic hardware/software partitioning, Proceedings of the 40th conference on Design automation , DAC '03, pp.250-255, 2003.
DOI : 10.1145/775832.775896
, Optimal selection theory for super concurrency, Proceedings of the 1989 Supercomputing Conference, pp.13-17, 1989.
, Heterogeneous Supercomputing: Problems and Issues, Proceedings. Workshop on Heterogeneous Processing, pp.3-12, 1992.
DOI : 10.1109/WHP.1992.664379
URL : http://scholarworks.rit.edu/cgi/viewcontent.cgi?article=1320&context=other
, Heterogeneous computing: challenges and opportunities, Computer, vol.26, issue.6, pp.18-27, 1993.
DOI : 10.1109/2.214439
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.477.3111
, PAWS: a performance evaluation tool for parallel computing systems, Computer, vol.24, issue.1, pp.18-29, 1991.
DOI : 10.1109/2.67190
, Heterogeneous computing Annual Research Summary 5, 1994.
, Estimation of Execution times on Heterogeneous Supercomputer Architectures, 1993 International Conference on Parallel Processing, ICPP'93 Vol1, pp.219-226, 1993.
DOI : 10.1109/ICPP.1993.80
, DSC: scheduling parallel tasks on an unbounded number of processors, IEEE Transactions on Parallel and Distributed Systems, vol.5, issue.9, pp.951-967, 1994.
DOI : 10.1109/71.308533
, Predictability of process resource usage: a measurement-based study on UNIX, IEEE Transactions on Software Engineering, vol.15, issue.12, pp.1579-1586, 1989.
DOI : 10.1109/32.58769
, Run-time statistical estimation of task execution times for heterogeneous distributed computing, Proceedings of 5th IEEE International Symposium on High Performance Distributed Computing HPDC-96, pp.263-270, 1996.
DOI : 10.1109/HPDC.1996.546196
, Studies in the useful predictability of programs in a distributed and homogeneous environment. The Smartnet Home Page, p.80, 1995.
, Statistical Prediction of Task Execution Times Through Analytic Benchmarking for Scheduling in a Heterogeneous Environment, 1999.
, Predicting the Resource Requirements of a Job Submission, Computing in High Energy Physics, p.273, 2004.
, Dynamic and On-line Design Space Exploration for Reconfigurable Architectures, To appear in the special issue of the HiPEAC Transactions on High-Performance Embedded Architecture and Compilers
, An efficient on-line Approach for On-Chip HW/SW Partitionner and Scheduler " , to appear in DRS Workshop, pp.12-17, 2006.
, An Adaptive On-Line HW/SW Partitioning for Soft Real Time Reconfigurable Systems, 8th Euromicro Conference on Digital System Design (DSD'05), 2005.
DOI : 10.1109/DSD.2005.12
, Auguin, « On line HW/SW Partitioning and scheduling for data dependent execution time applications, 30th EUROMICRO Conference/Proceedings of the Work In Progress Session, pp.43-44, 2004.
, Algorithme de prédictions statistiques du temps d'exécution basée sur la méthode de KPPV, IEEE Int congrès SCS, pp.265-271, 2004.
, HW/SW Partitioning of Embedded Applications with Variable execution time on a Reconfigurable Architecture, IEEE Int. Conf. SSD, pp.26-28, 2003.
, Algorithms for the partitioning of applications containing variable duration tasks on reconfigurable architectures, ACS/IEEE International Conference on Computer Systems and Applications, 2003. Book of Abstracts., pp.14-18, 2003.
DOI : 10.1109/AICCSA.2003.1227450
, Execution Time Assessment of an Application on a Heterogeneous Architecture. Case of Study: Motion Detection, Conf. SSD 2005 Sousse, pp.21-24, 2005.
, ABID Approche de partitionnement en ligne d'applications à temps d'exécution variable, Renpar'15 /ASF/SYMPAAA, pp.365-371, 2003.
, Etude du partitionnement logiciel/matériel d'applications à distribution variable de charge de calcul, pp.334-338, 2002.
, Partitionnement d'applications à temps d'exécution variable sur architectures reconfigurables, 2002.
, Portage d'un noyau multitâche temps réel sur un processeur embarqué, GEI, 2003.