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Optimisations Mémoire dans la méthodologie « Adéquation Algorithme Architecture » pour Code Embarqué sur Architectures Parallèles

Abstract : In the field of embedded electronics, the applications of digital communications and image processing induce very strong time constraints while allowing a limitation in resources and performances of the computation units. The restriction of the memory usable can be in opposite of fields such as video coding. A solution to achieve a real-time implementation can be reached through a distribution on a parallel architecture. These problems are the framework of this work. More precisely, that is why we developed a process of rapid prototyping dedicated to the parallel architectures with several processors of digital signal processing of the last generation (FPGA, DSP). The optimization aspect of the allocated memory is performed here in a more precise way.
The prototyping process was elaborate around SynDEx, a tool developed with the INRIA, based on the AAA methodology. This process aims at improving the implementation of an algorithm on a multi-component architecture by determining an optimal distribution and scheduling. SynDEx carries out the adequation phase itself, and generates an executive independent of the target. We initially contributed to the automation of the process on multiprocessors target, by adding a functional layer, and by developing new specific kernels for processors of digital signal.
In an embedded context, our concerns are then the minimization of the memory for the generated code. It is still a problem very open for multi-component architectures. The found solution, thanks to the algorithms of colouring of graph, leads to a significant improvement of the results of distributed implementation. The rapid prototyping towards multi-component platforms is automatic today, and memory optimizations are directly integrated in the SynDEx tool.
Another part of this work related to the development and integration, through our prototyping process, of consequent applications in the fields both of the image processing (MPEG-4, LAR) and both of the telecommunications (MC-CDMA, UMTS). Results validate the whole process, and show its adaptation to systems oriented data processing. The report is concluded on new perspectives, while being interested in particular in multi-layer systems linking together several layers: a “transport” layer of telecommunication and a “service” layer of image processing.
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Contributor : Mickaël Raulet <>
Submitted on : Friday, January 12, 2007 - 5:26:51 PM
Last modification on : Monday, December 14, 2020 - 12:28:23 PM
Long-term archiving on: : Tuesday, April 6, 2010 - 7:59:44 PM


  • HAL Id : tel-00124276, version 1



Raulet Mickaël. Optimisations Mémoire dans la méthodologie « Adéquation Algorithme Architecture » pour Code Embarqué sur Architectures Parallèles. domain_other. INSA de Rennes, 2006. Français. ⟨tel-00124276v1⟩



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