Abstract : This thesis is dedicated to thé implémentation of PEPSys (Parallel ECRC Prolog System) on a shared memory multiprocessor and to thé évaluation of this implémentation. The PEPSys project aims at exploiting thé parallelism in logic programming to obtain, on existing multiprocessors, performance improvements compared to efficient sequential Prolog implémentations. A language, extension of Prolog, a computational model and an abstract machine based on thé WAM have been defined and validated by a multiprocessor implémentation and a simulator of extensible architectures. The computational model supports OR and independent AND parallelisms and thé combination of both with sequential exécution and backtracking. The implémentation of PEPSys which is thé main topic of this thesis, is one of thé first OR-parallel logic systems to provide efficiency improvements, compared to state of thé art Prolog systems. The numerous measures provided in this thesis allow to validate this implémentation and thé main design décisions of thé computational model, while suggesting improvements.