Vérification formelle des systèmes numériques par démonstration de théorèmes: application aux composants cryptographiques

Abstract : Due to the growing complexity of SoC, the verification became a very important aspect: 70-80% of the design cost is allocated to this task. More than 60% of the ASIC development projects have to be remade because of functional errors - 50% of the functional errors are at the module level. In the industry, verification is synonym with simulation – a natural verification method for the designers, but it does not guarantee the absence of the errors. An alternative is formal verification, which proves mathematically that a circuit satisfies a specification. In this thesis we are interested in deductive methods based on theorem proving. Theorem proving is generally used for the formal verification of high level or complex designs, as the size of data is not important. The inconvenient is that the model of the design is described directly in the logic of the tool, which makes the access to the technique very difficult for the designers. The goal of our work is to facilitate the introduction of such tools in the design flow. We propose an automatic method to translate a VHDL design to a semantic model based on recurrent equations on time, which can be the input to any theorem proving tool and we define a verification approach adapted to the model. To validate our proposal, we chose ACL2 as tool to verify a cryptographic library.
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https://tel.archives-ouvertes.fr/tel-00104174
Contributor : Lucie Torella <>
Submitted on : Friday, October 6, 2006 - 9:02:52 AM
Last modification on : Wednesday, May 16, 2018 - 6:30:03 PM
Long-term archiving on : Tuesday, April 6, 2010 - 6:38:16 PM

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  • HAL Id : tel-00104174, version 1

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D. Toma. Vérification formelle des systèmes numériques par démonstration de théorèmes: application aux composants cryptographiques. Autre [cs.OH]. Université Joseph-Fourier - Grenoble I, 2006. Français. ⟨tel-00104174⟩

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