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Abstract : The probability of transient faults increases with the evolution of the technologies. Several approaches have been proposed to early analyze the impact of these faults in a digital circuit. It is in particular possible to use an approach based on the injection of faults in a RT-Level VHDL description. In this thesis, we make several contributions to this type of analysis. A first considered aspect is to take into account the digital circuit's environment during the injection campaigns. So, an approach based on multi-level dependability analysis has been developed and applied to an example. The injections are performed in the digital circuit described at the RT-Level while the rest of the system is described at a higher level of abstraction. The results' analysis shows that failures appearing at circuit's level have in fact no impact on the system. We then present the advantages of the combination of two types of analyses : classification of faults with respect to their effects, and a more detailed analysis of error configurations activated in the circuit. An injection campaign of SEU-like faults was performed on a 8051 microcontroller described at RT-Level. The results show that the combination of the two type analyses allows a designer to localize the critical points, facilitating the hardening stage. They also show that, in the case of a general processor, the error configurations can be dependent on the executed program. This study also demonstrates that injecting a very small percentage of the possible faults gives useful information to the designer. The same methodology has been used to validate the robustness obtained with a software hardening. The results show that some faults are not detected by the implemented mechanisms although those were previously validated by fault injections based on an instruction set simulator. The last aspect of this thesis concerns the fault injection in analog blocks. In fact very few works cover this subject. We thus propose a global analysis flow for digital, analog or mixed circuits, described at behavioral level. The possibility to inject faults in analog blocks is discussed. The results obtained on a PLL, chosen as case study, have been analysed and show the feasibility of fault injections in analog blocks. To validate this flow, fault injections were also performed at transistor level and compared to those performed at high level. It appears a good correlation between the results obtained at the two levels.
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Contributor : Lucie Torella <>
Submitted on : Wednesday, September 27, 2006 - 4:41:43 PM
Last modification on : Friday, December 11, 2020 - 8:28:03 AM
Long-term archiving on: : Tuesday, April 6, 2010 - 1:15:47 AM


  • HAL Id : tel-00101622, version 1




A. Ammari. ANALYSE DE SÛRETE DES CIRCUITS COMPLEXES DECRITS EN LANGAGE DE HAUT NIVEAU. Micro et nanotechnologies/Microélectronique. Institut National Polytechnique de Grenoble - INPG, 2006. Français. ⟨tel-00101622⟩



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