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Plate-forme de prototypage rapide fondée sur la synthèse de haut niveau pour applications de radiocommunications.

Pierre Bomel 1
1 Lab-STICC_UBS_CACS_MOCS
Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance
Abstract : Semi-conductor very deep sub-micron technologies available today and single-die system integration complexity increase raise new methodological challenges in system design activities. Intensive reuse of pre-developed, or synthesized on demand, components reduce development time and thus design cost. Unfortunately, this reuse paradigm creates critical paths on long metallic wires between components. Local frequency optimization of each bloc can be lost when the inter-component communication network has poor performances. The theory of latency insensitive systems (LIS) recommends in this context a very promising solution based on a pseudo-asynchronous communication network and on synchronization wrapper models which encapsulate components and make them robust (insensible) to the communication asynchronisms. Nevertheless, one must state that the different wrapper architecture proposals are not speed and area efficient enough to be deployed in all conditions. This is particularly true when components have long computation latencies and process huge amount of data as we commonly find in digital radio-communications.
We propose in this work a rapid prototyping platform architecture named PALMYRE. It is dedicated to digital radio-communications and integrates into its system platform part a new version of the high-level synthesis tool GAUT. We first study computing and communication constraints for DVB-DSNG applications. Secondly, we survey the most recent prototyping methodologies and we take a count of the current prototyping platforms in use. We retain the platform based prototyping/design methodology as the most sound basis and rely on its tree steps architecture (hardware, software and system platforms) to guide our platform design. The platform we propose is composed of computing nodes (C6x DSPs and VirtexE FPGAs) and point to point communication links able to reach a sustained bandwidth of 3 Gbit/s. We develop a C++ API for the DSPs and VHDL hardware interfaces which allow a mixed DSP/FPGA prototype to efficiently communicate between nodes. We also propose an API performances characterization method enabling to determine best running conditions in term of memory, packet size and communication programming style (synchronous vs asynchronous).
The integration of GAUT into the system platform allows to semi-automatically synthesize components specified at the algorithmic level. These are also called virtual IPs. They naturally communicate through our API and hardware interfaces and exploit the computing and communication resources from the hardware and software platforms. This integration into a CAD flow is possible thanks to two distinct contributions. First, we introduce the theory of latency insensitive systems inside the communication units synthesized by GAUT. It allows to preserve the local frequency optimizations of components when designing a whole system with synthesized IPs. To reach this objective we present a new wrapper model and call it a synchronization processor. We prove experimentally its better speed and area performances compared to the current best finite state machines architectures of wrappers. Then, we design a new multi-banks memory unit which main benefit is to support the algorithmic-level pipelining introduced by GAUT when simple hardware parallelism is not sufficient to sustain an applicative sampling cadency. This memory unit handles data transfers for all pipeline stages and dynamic address computation while accessing the different instances of duplicated variables.
Thanks to these new communication and memory units, GAUT is successfully used in a project targeting the design of a DVB-DSNG modem. This is the RNRT ALIPTA project. The companies Arexsys, Sacet, Thales Communications and Turboconcept whith the ENSTB and the LESTER have worked on several digital IPs and validated their integration into an existing DVB-DSNG processing chain. A close study of synthesis results proves that up to 90% of area savings and from 10 to 30% of frequency increase can be obtained when the wrappers are implemented with our synchronization processors. We conclude that, in the context of a system design methodology based on intensive virtual IP reuse, area reduction, optimal frequencies preservation, easier composition of processing chains based on synchronous blocs and possibility to migrate to multi-chips modules solutions are four key advantages enabled by the integration of GAUT in the PALMYRE system platform.
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Submitted on : Thursday, September 7, 2006 - 9:23:52 AM
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Pierre Bomel. Plate-forme de prototypage rapide fondée sur la synthèse de haut niveau pour applications de radiocommunications.. Micro et nanotechnologies/Microélectronique. Université de Bretagne Sud, 2004. Français. ⟨tel-00091710⟩

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