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REDUCTION DE PUISSANCE DURANT LE TEST PAR SCAN DES CIRCUITS INTEGRES

Abstract : This thesis relates to power minimization during scan testing. The Scan technique is considered as the most often used DfT (Design for Test) technique. During test, scan-based architectures require a large number of operations to load, apply, and unload test data. All these operations produce a switching activity which is much higher than that during functional mode. For this purpose, we propose several solutions to minimize the power consumption during scan testing, and particularly during the period of time comprised between the application of a test vector and the capture of the circuit response. These solutions allow safe and no destructive testing of the circuit under test.
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https://tel.archives-ouvertes.fr/tel-00091300
Contributor : Nabil Badereddine <>
Submitted on : Monday, September 18, 2006 - 5:30:06 PM
Last modification on : Thursday, May 24, 2018 - 3:59:21 PM
Long-term archiving on: : Monday, September 20, 2010 - 4:22:32 PM

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  • HAL Id : tel-00091300, version 2

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Nabil Badereddine. REDUCTION DE PUISSANCE DURANT LE TEST PAR SCAN DES CIRCUITS INTEGRES. Micro et nanotechnologies/Microélectronique. Université Montpellier II - Sciences et Techniques du Languedoc, 2006. Français. ⟨tel-00091300v2⟩

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