. Nomadik, com/stonline/prodpres/dedicate/proc/proc.htm [ 3 ]Nexperia, http://www.semiconductors.philips.com/products/nexperia

M. Aoe-group, Proposal Package Description (PPD) -Revision 3, Doc. ISO/IEC JTC1/SC29/WG11 N998, Tokyo meeting, 1995.

F. Pereira, MPEG-4: a new challenge for the representation of audio-visual information, Keynote speech at Picture Coding Symposium' 96, 1996.

N. Ik-cho, D. Yun, and S. U. Lee, A Fast Algorithm for 2D-DCT, International Conference on Acoustics, Speech and Signal Processing (ICASSP), p.2197, 1991.

A. M. Tourapis, Optimizing the MPEG4 encoder ? Advanced diamond zonal search, IEEE International Symposium for Circuits and Systems, pp.674-677

C. Jian-wen-chen, Y. Kao, and . Lin, Introduction to H.264 Advanced Video Coding Asian and South Pacific Design and Automation Conference, pp.736-741, 2006.

S. W. Golomb, Run-length encoding, IEEE Trans. On Inf. Theory, pp.399-401, 1966.

D. Huffman, A method for the construction of minimum redundancy codes, Proceedings of IRE, pp.1098-1101, 1952.

P. Paulin, Parallel programming models for a multi-processor SoC platform applied to high-speed traffic management, Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis , CODES+ISSS '04, pp.48-53, 2004.
DOI : 10.1145/1016720.1016735

Y. He, A Software Based MPEG-4 Video Encoder Using Parallel Processing, IEEE Trans. on Circuits and Systems for Video Tech, vol.8, issue.7, pp.909-920, 1998.

M. Yadav, G. Venkat, and B. L. Evans, Modeling and Simulation on H.26L Encoder, Final Report for EE382C Embedded Software Systems, 2002.

M. Raulet, Automatic coarse-grain partitioning and automatic code generation for heterogeneous architectures, 2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682), 2003.
DOI : 10.1109/SIPS.2003.1235689

URL : https://hal.archives-ouvertes.fr/hal-00124965

M. Wassim-youssef, S. Yoo, A. Sasongko, Y. Paviot, and A. Jerraya, Debugging HW/SW Interface for Multiprocessor SoC: Video Encoder System Design Case, pp.908-913, 2004.

P. Van and . Wolf, Design and Programming of Embedded Multiprocessors: An Interface-Centric Approach, CODES-ISSS, pp.206-217, 2004.

M. N. Satya-kiran, A Complexity Effective Communication Model for Behavioural Modelling of Signal Processing Applications, pp.412-415, 2003.

L. Formaggio, A timing-accurate HW/SW co-simulation of an ISS with SystemC, Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis , CODES+ISSS '04, pp.152-157, 2004.
DOI : 10.1145/1016720.1016759

C. Chiang, High-Level Heterogenous Distributed Parallel Programming, Proceedings of the 2004 international symposium on Information and communication technologies, pp.250-255, 2004.

M. Portable and M. Implementation, M4 -a GNU implementation of the UNIX macro processor

L. Lavagno, Specification, Modelling and Design Tools for System-on- Chip, ASP-DAC 2002/VLSI Design, 2002.

C. Wolinski, M. Gokhale, and K. Mccabe, A polymorphous computing fabric, IEEE Micro, vol.22, issue.5, pp.56-68, 2002.
DOI : 10.1109/MM.2002.1044300

S. Solden, Architectural Services Modeling for Performance in HW-SW Codesign, Proceedings of the Workshop on Synthesis And System Integration of Mixed Technologies, pp.72-77, 2001.

S. I. Han, A. Baghdadi, M. Bonaciu, S. I. Chae, and A. A. Jerraya, An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory, Proceedings of the 41st annual conference on Design automation , DAC '04, pp.250-255, 2004.
DOI : 10.1145/996566.996636

URL : https://hal.archives-ouvertes.fr/hal-00008046

G. Lovic, Génération de système d'exploitation pour le ciblage de logiciel multitâche sur des architectures multiprocesseurs hétérogènes dans le cadre des systèmes embarqués spécifiques, 2001.

W. Cesario, Y. Paviot, A. Baghdadi, G. Lovic, L. Damian et al., HW/SW interfaces design of a VDSL modem using automatic refinement of a virtual architecture specification into a multiprocessor SoC: a case study, Design Automation and Test in Europe (DATE'02), pp.165-169, 2002.
URL : https://hal.archives-ouvertes.fr/hal-01380859

G. Nicolescu, Spécification et validation des systèmes hètèrogènes embarqués, 2002.

W. Cesario, G. Nicolescu, L. Gauthier, D. Lyonnard, and A. Jerraya, Colif: A multilevel design representation for application-specific multiprocessor system-on-chip design, Proceedings 12th International Workshop on Rapid System Prototyping. RSP 2001, pp.110-116, 2001.
DOI : 10.1109/IWRSP.2001.933847

URL : https://hal.archives-ouvertes.fr/hal-00008079

P. Yanick, Partitionnement des services de communication en vue de la génération automatique des interfaces logicielles/matérielles, 2004.

A. Sarmento, Génération automatique de modèles de simulation pour la validation de systèmes hétérogènes embarqués, 2005.

A. A. Jerraya and W. Wolf, Multiprocessor Systems-on-Chips, 2004.
URL : https://hal.archives-ouvertes.fr/hal-00012749

C. Tung-chien-chen, L. Lian, and . Chen, Hardware architecture design of an H.264/AVC video codec, Asia and South Pacific Conference on Design Automation, 2006., pp.750-757, 2006.
DOI : 10.1109/ASPDAC.2006.1594776

H. Lin, Y. Wang, K. Cheng, S. Yeh, W. Chen et al., Algorithms and DSP Implementation of H, 11 th Asian and South-Pacific Design Automation Conference, pp.742-749, 2006.

J. Sung-dae-kim, C. J. Hoo-lee, M. H. Hyun, and . Sunwoo, ASIP Approach for Implementation of H, 11 th Asian and South-Pacific Design Automation Conference, ASP-DAC 2006, pp.758-764, 2006.

M. Omer-cheema and O. Hammami, Customized SIMD unit synthesis for system on programmable chip: a foundation of HW/SW partitioning with vectorization, 11 th Asian and South-Pacific Design Automation Conference, ASP-DAC 2006, pp.54-60, 2006.

S. Braunl, W. Feyrer, H. Rapf, M. Walischmiller, and . Reinhardt, Parallel Image Processing, 1300.
DOI : 10.1007/978-3-662-04327-1

D. Zmaranda and M. Bonaciu, Data Structures and Advanced Programming Techniques, 2003.

L. Kriaa, Modélisation et Validation des systèmes hétérogènes : Définition d'un modèle d'exécution, 2005.

M. Wassim and Y. , Etudes des interfaces logicielles/matérielles dans le cadre des systèmes multiprocesseurs monopuces et des modèles de programmation parallele de haut niveau, 2006.

H. Posadas, F. Herrera, P. Sánchez, E. Villar, and F. Blasco, System-level performance analysis in SystemC, Proceedings Design, Automation and Test in Europe Conference and Exhibition, pp.378-383, 2004.
DOI : 10.1109/DATE.2004.1268876

H. Posadas, J. Ádamez, P. Sánchez, E. Villar, and F. Blasco, POSIX modeling in SystemC, 11 th Asian and South-Pacific Design Automation Conference, pp.485-490, 2006.

F. Dumitrascu, I. Bacivarov, L. Pieralisi, M. Bonaciu, and A. Jerraya, Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application, Proceedings of the Design Automation & Test in Europe Conference, pp.166-171, 2006.
DOI : 10.1109/DATE.2006.243843

URL : https://hal.archives-ouvertes.fr/hal-00105184

A. Bouchima, I. Bacivarov, W. Youssef, M. Bonaciu, and A. Jerraya, Using abstract CPU subsystem simulation model for high level HW/SW architecture exploration, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005., pp.372-377, 2005.
DOI : 10.1109/ASPDAC.2005.1466501