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Algorithmique du décalage d'instructions

Guillaume Huard 1, 2 
2 MOAIS - PrograMming and scheduling design fOr Applications in Interactive Simulation
ID-IMAG - Informatique et Distribution, Inria Grenoble - Rhône-Alpes, UJF - Université Joseph Fourier - Grenoble 1
Abstract : The constant evolution of processors architectures, with superscalar, instruction-level parallelism, prediction and speculation capabilities and the multiple number of levels in the memory hierarchy give an increasing importance to the work of the compiler.
In this thesis we deal with source program transformations, intended to optimization within the compilation process, and especially with a transformation known as loop shifting.
This transformation is used as a basis for software pipelining, it has an incidence on the instruction level parallelism and registers usage.
It is also involved as a component of loop parallelization techniques based on affine schedules.
In this thesis we have tried to reach a better understanding of the possibilities that loop shifting has to offer, to know which goals it is able to score, and which problems remain hard.
To this intent, we have studied loop shifting within a variety of contexts, more or less close to each other, and we provide a contribution for each of them.

In the context of software pipelining, we give a polynomial algorithm to find the loop shifting leading to as much instruction-level parallelism as possible, and we perform an experimental study of its absolute efficiency, with the help of PASTAGA (french translation of ``Platform for statistical analysis and algorithms testing on random graphs''), a tool we developed for this purpose.
In the contexts of register usage (stage scheduling), loop parallelization and locality, we give answers in each case to loop shifting problems: complexity, exact solutions and heuristics.
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Submitted on : Monday, July 10, 2006 - 3:01:56 PM
Last modification on : Wednesday, February 2, 2022 - 3:54:49 PM
Long-term archiving on: : Monday, April 5, 2010 - 10:10:50 PM


  • HAL Id : tel-00084753, version 1



Guillaume Huard. Algorithmique du décalage d'instructions. Autre [cs.OH]. Ecole normale supérieure de lyon - ENS LYON, 2001. Français. ⟨tel-00084753⟩



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