, High-level synthesis under I/O Timing and Memory constraints, 2005 IEEE International Symposium on Circuits and Systems, 2005.
DOI : 10.1109/ISCAS.2005.1464679
URL : https://hal.archives-ouvertes.fr/hal-00077297
, A More Efficient and Flexible DSP Design Flow from Matlab-Simulink, Proceedings. (ICASSP '05). IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005., pp.61-64, 2005.
DOI : 10.1109/ICASSP.2005.1416240
URL : https://hal.archives-ouvertes.fr/hal-00077301
, High Level Ageing Vectors Management for Data Intensive Applications, Proceedings of ICSES (International Conference on Signal and Electronic Systems), 2004.
URL : https://hal.archives-ouvertes.fr/hal-00077305
, Memory accesses management during high level synthesis, Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis , CODES+ISSS '04, pp.42-47, 2004.
DOI : 10.1145/1016720.1016733
URL : https://hal.archives-ouvertes.fr/hal-00077355
, Memory aware HLS and the implementation of ageing vectors, Euromicro Symposium on Digital System Design, 2004. DSD 2004., pp.88-95, 2004.
DOI : 10.1109/DSD.2004.1333262
URL : https://hal.archives-ouvertes.fr/hal-00077366
, A Memory Aware behavioral Synthesis Tool for Real-Time VLSI Circuits Memory Aware High-Level Synthesis for Embedded Systems, Proceedings of ACM GLSVLSI (Great Lake Symposium On Very Large Scale Integration) Proceedings of IADIS Applied Computing, pp.82-85, 2004.
, A memory aware high level synthesis tool, IEEE Computer Society Annual Symposium on VLSI, pp.279-280, 2004.
DOI : 10.1109/ISVLSI.2004.1339557
URL : https://hal.archives-ouvertes.fr/hal-00077377
, Synthèse Comportementale Sous Contraintes de Communication et de Placement Mémoire pour les composants du TDSI Réduction de l'influence du placement mémoire par la synthèse de haut niveau, Proceedings of GRETSI'05 (Colloque sur le Traitement du Signal et de l'Image), sept 2005. [Corr05b] Gwenolé Corre Proceedings of FTFC'05 (journées d'études Faible Tension Faible Consommation), 2005.
, Contraintes mémoire et solution architecturale pour applications TDSI Ordonnancement sous contraintes de mémorisation : une optimisation efficace des ressources lors de la synthèse d'architecture, Proceedings of GRETSI (Colloque sur le Traitement du Signal sept 2003. [Corr03b] Gwenolé Corre Proceedings of FTFC (journées d'études Faible Tension Faible Consommation), pp.147-152, 2003.
, Intégration de la synthèse mémoire dans l'outil de synthèse d'architecture GAUT Low Power, Proceedings of JFAAA (Journée Francophone sur l'Adéquation Algorithme Architecture), 2002.
, Optimisation de la consommation des unités de mémorisation lors de la synthèse d'architecture, Proceedings of GDR-CAO, pp.169-172, 2002.
, The SUIF compiler for scalable parallel machines, Proceedings of the 7th SIAM Conference on Parallel Proceedings for Scientific Computing, pp.662-667, 1995.
, Polynomial-Time Algorithm for On-Chip Scratchpad Memory PartitioningAn Optimal Memory Allocation Scheme for Scratch-Pad-Based Embedded Systems, Proceeding on CASES, pp.318-326, 2002.
, Compiler transformation for high performance computingMéthodologie de synthèse des unités de communication matérielles dans une approche de conception mixte logiciel/matériel (codesign )," Thèse de l'université de Rennes I, décembre 1997A Formal Technique for Hardware Interface design, IEEE Transactions On Circuits And Systems, pp.345-420, 1994.
, Allocation of multiport memories in data path synthesis, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp.536-540, 1988.
DOI : 10.1109/43.3188
, LeZi-Update : An Information-Theoretic Approach to Track Mobile Users in PCS NetworksSystematic Cycle budget versus System Power Trade-off: a New Perspective on System Exploration of Real-time Data-dominated Applications, Proceedings of the 5th Annual ACM/IEEE International Conference on Mobile Computing and Networking (MobiCom'99) Proceedings of IEEE Intnl. Symp. on Low Power Design, pp.1-12, 1999.
, Reed-Solomon behavioral virtual component for communication systems, Proceedings of IEEE International Symposium on Circuits and Systems, pp.21-23, 2004.
, Data access and storage management for embedded programmable processors, 2002.
DOI : 10.1007/978-1-4757-4903-8
, Custom Memory Management Methodology : Exploration of Memory Organisation for Embedded Multimedia System Design, 1998.
, Méthodologie de conception architecturale des mémoires pour circuits dédiés au traitement du signal temps réel Thèse de Doctorat de l'Université de Rennes I, JanvierOn Caching and Prefetching of Virtual Objects in Distributed Virtual Environments, Proceedings of the 6 th ACM International Conference on Multimedia (Multimedia'98), pp.171-180, 1997.
, Communication and Timing Constraints Analysis for IP Design and Integration, Proceedings of IFIP WG 10.5 Very Large Scale Integration of System-on-Chip (VLSI- SOC) Conference, pp.38-43, 2003.
, Synthèse d'Interface de Communication pour les Composants Virtuels, Thèse de Doctorat de l, 2003.
, A preprocessing step for global loop transformations for data transfer and storage optimization, Proceedings of Intnl. Conference on Compilers, Arch. and Synth. for Embedded Systems, pp.34-40, 2000.
, Formalized methodology for data reuse exploration in hierarchical memory mappings, Proceedings of IEEE Intnl. Symp. on Low Power Design, pp.30-35, 1997.
, Some Computer Organizations and Their Effectiveness, IEEE Transactions on Computers, volume C-21, pp.948-960, 1972.
DOI : 10.1109/TC.1972.5009071
, High-Level Synthesis : Introduction to Chip and System Design Access Pattern based Local Memory Customization for Low Power Embedded Systems, Proceedings of DATE conference, pp.778-784, 1991.
DOI : 10.1007/978-1-4615-3636-9
, Architecture des ordinateurs : une approche quantitative
, Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch BuffersAn Integrated Cache Timing and Power Model, Proceedings of the 17th Annual International Symposium on Computer Architecture, pp.364-373, 1990.
, Analytical energy dissipation models for low power caches, Proceedings of int. Symp. On low power electronic and design, pp.143-148, 1997.
, Compiler-Directed Scratch Pad Memory Hierarchy Design and Management, Proceedings of DAC, pp.628-633, 2002.
DOI : 10.1145/514074.514077
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.12.1532
, Definition and solution of the memory packing problem for field-programmable systems, Proceedings of the IEEE/ACM International Conference on Computer Aided Design, pp.20-26, 1994.
, Utilization of multiport memories in data path synthesis, Proceedings of the 30th international on Design automation conference , DAC '93, pp.298-302, 1993.
DOI : 10.1145/157485.164900
, Behavioral synthesis methodology for HDL-based specification and validation, Proceedings of the 32nd ACM/IEEE conference on Design automation conference , DAC '95, pp.286-291, 1995.
DOI : 10.1145/217474.217543
, Assignment of global memory elements for multi-process vhdl specifications, Proceedings of the International Conference on Computer Aided Design, pp.496-501, 1992.
, Constrained Resource Sharing and Conflict Resolution in Hebe, In Integration: the VLSI Journal, vol.12, issue.2, pp.131-166, 1991.
, Seer : Predictive File Hoarding for Disconnected Mobile Operation, Thèse de doctorat, 1997.
, Cache optimisation for multimedia application A scheduling algorithm for multiport memory minimization in datapath synthesis, Proceedings of the Conference on Asia Pacific Design Automation Conference, pp.93-100, 1995.
, An Analytical Approach to File Prefetching, Proceedings of the USENIX 1997 Annual Technical Conference, pp.275-288, 1997.
, Exploiting Off-Chip Memory Access Modes in High-Level Synthesis Memory optimization and exploration for embedded systems, Thèse, 1997.
, Memory Issues in Embedded Systems-On-Chip: Optimizations and Exploration, 1999.
DOI : 10.1007/978-1-4615-5107-2
, Local memory exploration and optimization in embedded systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.18, issue.1, pp.3-13, 1999.
DOI : 10.1109/43.739054
, Multi-dimensional interleaving for time-andmemory design optimization, Proceedings of IEEE Int. Conference On Computer Design, pp.440-445, 1995.
, Informed Prefetching and Caching, Proceedings of the 15th ACM Symposium on Operating System Principles (SOSP'95), pp.79-95, 1995.
, From Digital Signal Processing Specification to Layout, Proceedings on Logic and Architecture Synthesis : state-of-the-art and novel approaches, pp.307-313, 1995.
, Optimisation de la consommation d'énergie des applications de Traitements Du Signal et de l'Image embarquées sur DSPOptimisation de la consommation des systèmes temps reel embarqués, Proceedings of journées FTFC Thèse de Doctorat de l, 2001.
, SoftExplorer: Estimation, Characterization, and Optimization of the Power and Energy Consumption at the Algorithmic LevelFast and extensive systemlevel memory exploration for ATM applications, Proc of PATMOS Conference Proceedings of 10th ACM/IEEE Intnl. Symp. on System-Level Synthesis, pp.342-351, 1997.
, L'ingénierie de production 50 fiches pour mieux produire ISBN : 2225823057, Edition MASSON, Collection Organisation IndustrielleAssigning Program and Data Objects to Scratchpad for Energy Reduction, Proceeding of DATE conference, pp.409-414, 1991.
, Reducing Energy Consumption by Dynamic Copying of Instructions onto Onchip Memory, Proceeding on ISSS, pp.213-218, 2002.
, Intelligent File Hoarding for Mobile Computers Storage Size Reduction by In-Place Mapping of ArraysCompiler-Decided Dynamic Memory Allocation for Scratch-Pad Based Embedded Systems, Proceedings of the 1st Annual ACM/IEEE International Conference on Mobile Computing and Networking (MobiCom'95) Proceedings of International Workshop on Verification, Model Checking and Abstract Proceeding of CASES conference, pp.119-125, 1995.
, Global Multimedia System Design Exploration using Accurate Memory Organization Feedback, Proceedings 36th ACM/IEEE Design Automation Conference, pp.327-332, 1999.
, Improved Force-Directed Scheduling in High-Throughput Digital Signal Processing Dynamic overlay of Srcatchpad Memory for Energy MinimizationMinimizing the required memory bandwidth in vlsi system realizations, IEEE Transactions on Computer-Aided Design Of Integrated Circuits and Systems IEEE Transactions on VLSI Systems, pp.945-960, 1995.
, 150 ns Boucle critique du GFD: 150 ns Temps sequentiel multifonction du GFD : 500 ns Temps sequentiel monofonction du GFD : 340 ns
, (@x(1)) (VIE) : Tdeb : 60, Tfin : 220, entree : memoire, sortie
, Tdeb : 10, Tfin : 40, entree : 1, sortie
, Tdeb : 40, Tfin : 300
, @h(2)0001) (LOC) : Tdeb : 100, Tfin : 110, entree : memoire, sortie : 3
, Tdeb : 60, Tfin : 70
, Tdeb : 80, Tfin : 90
, Tdeb : 100, Tfin : 110
, Tdeb : 120, Tfin : 130
, Tdeb : 140, Tfin : 150
, Tdeb : 180, Tfin : 190
, Tdeb : 200, Tfin : 210
, Tdeb : 220, Tfin : 230
, Tdeb : 240, Tfin : 250
, Tdeb : 260, Tfin : 270
, Tdeb : 280, Tfin : 290
, Tdeb : 300, Tfin, p.310
, Tdeb : 320, Tfin : 330
, Tdeb : 340, Tfin : 350
, Tdeb : 360, Tfin : 370
, Tdeb : 160, Tfin : 190
, Tdeb : 190, Tfin : 230, entree : 3, sortie : 3
, Tdeb : 230, Tfin : 270, entree : 3, sortie : 3
, Tdeb : 270, Tfin : 290, entree : 3, sortie : 3
, Tdeb : 290, Tfin : 330, entree : 3, sortie : 3
, Tdeb : 330, Tfin : 350, entree : 3, sortie : 3
, Tdeb : 350, Tfin : 370, entree : 3, sortie : 3
, 0001 (GLO) : Tdeb : 110, Tfin : 220, entree : 3, sortie