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Gestion des unités de mémorisation pour la synthèse d'architecture

Abstract : Systems handle more and more complex applications. Processing increases faster than storage capacities. Memory becomes a bottleneck since the quantity of information increases. In this context, it is crucial to efficiently manage memory all along the design flow especially during the high level synthesis that offers good optimization opportunities.
We propose a methodology to integrate the management of memory unit into our high-level synthesis flow. Data distribution and memory architecture is defined as set of constraints in our high-level synthesis design flow. We realize high-level synthesis under memory constraints to obtain a memory architecture and its associated address generators.
We extend our methodology; it leads to a generic memory architecture to store specific data of DSP applications. We also introduced memory access management based on the kanban system that improves the anticipation of memory accesses.
Our methodology of synthesis under memory constraints and memory management of data in DSP application are integrated into our high level design flow and our tool GAUT. The proposed methodology could be extended to others domains.
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Contributor : Gwenolé Corre <>
Submitted on : Tuesday, May 30, 2006 - 11:07:06 AM
Last modification on : Friday, October 23, 2020 - 4:36:40 PM
Long-term archiving on: : Monday, April 5, 2010 - 9:47:56 PM


  • HAL Id : tel-00077288, version 1



Gwenolé Corre. Gestion des unités de mémorisation pour la synthèse d'architecture. Micro et nanotechnologies/Microélectronique. Université de Bretagne Sud, 2005. Français. ⟨tel-00077288⟩



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