Dynamically Configurable Security for SRAM FPGA Bitstreams, In Publication in International Journal of Embedded Systems ,
Dynamically Configurable Security for SRAM FPGA Bitstreams, pp.26-43, 2004. ,
Communication Costs Driven Design Space Exploration for Reconfigurable Architectures, the 13 th International Conference Field Programmable Logic and Applications, FPL'03, 2003. ,
DOI : 10.1007/978-3-540-45234-8_89
Fast Design Space exploration Method for Reconfigurable Architectures, Proceedings of International Conference of Engineering of Reconfigurable Systems and Algorithms, ERSA'03, 2003. ,
Low Complexity Design Space Exploration from Early Specifications, Revision Process in IEEE Transaction on Computer Aided Design, 2004. ,
Fast prototyping of reconfigurable architectures from a C program, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03., pp.25-28, 2003. ,
DOI : 10.1109/ISCAS.2003.1206381
Targeting Tiled Architectures in Design Exploration, 10th Reconfigurable Architectures Workshop, RAW03, Workshop of IPDPS 03, 2003. ,
A Modeling Method for Reconfigurable Architectures, IEEE International Workshop on System-on- Chip for Real-Time Applications, IWSOC'02, 2002. ,
DOI : 10.1007/978-1-4615-0351-4_16
Flot d'xeploration des architectures reconfigurables Journée Francophones sur l'Adéquation Algorithme Architecture, 2002. ,
Vers une approche unifiée pour la conception globale des terminaux de télécommunications Journée Francophones sur l'Adéquation Algorithme Architecture, 2002. ,
Méthode d'estimation relative des performances des architectures de FPGA, Colloque CAO, pp.15-16, 2002. ,
Reconfigurable Architecture Modeling. The THF Model, Application to the aSoC Architecture, 2002. ,
Exploration de l'espace de conception de l'architecture des circuits intégrés, ou comment construire une ville nouvelle, 2002. ,
Modélisation d'architectures reconfigurables embarquées, 2001. ,
Ultra-Low-Power Domain-Specific Multimedia Processors, Proceedings of the IEEE VLSI Signal Processing Workshop, 1996. ,
A Low-Power multiprocessor Architecture for Embedded Reconfigurable Systems. International Workshop on Power and Timing Modeling, Optimization and Simulation, 1998. ,
The Effect of LUT and Cluster Size on Depp-Submicron FPGA Performance and Density, International ACM Symposium on Field Programmable Gate Arrays, FPGA 00, pp.3-12, 2000. ,
FPSLIC Series, Field Programmable Systeme Level Integrated Circuit, 2003. ,
Partitionning and CoDesign Tolls & Methodology for Reconfigurable Computing : the EPICURE Philosophy, Proceeding of the Third International Workshop on Systems, 2003. ,
CODEF: a system level design space exploration tool, 2001 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.01CH37221), pp.1145-1148, 2001. ,
DOI : 10.1109/ICASSP.2001.941124
Large exploration for hw/sw partioning of multirate and aperiodic real-time systems, International Symposium on Hardware/Software Codesign (CODES), 2002. ,
Design space exploration for hardware/software codesign of multiprocessor systems, Proceedings 11th International Workshop on Rapid System Prototyping. RSP 2000. Shortening the Path from Specification to Prototype (Cat. No.PR00668), pp.8-13, 2000. ,
DOI : 10.1109/IWRSP.2000.854975
Bakground Memory Area Estimation for Multidimensional Signal Processing Systems, IEEE Transactions on VLSI Systems, pp.157-172, 1995. ,
PACT- XPP -A Self-reconfigurable Data Processing Architecture, proceeding of the International Conference of Engineering of Reconfigurable Systems and Algorithms, ERSA 01, 2001. ,
Caractérisation d'Architectures Reconfigurables, Le Systolic Ring. Journées Francophones Adéquation Algorithme Architecture, JFAAA'02, pp.16-18, 2002. ,
Metrics for Reconfiguration Architectures Characterization : Remanece and Scalability, 10th Reconfigurable Architectures Workshop, RAW03, Workshop of IPDPS 03, 2003. ,
The Esterel v5 Language Primer, Version v5-91, 2000. ,
VPR and T-Vpack User's Manual (Version 4.30), 2000. ,
Architecture and CAD for Deep Submicron FPGAs, 1999. ,
DOI : 10.1007/978-1-4615-5145-4
VPR: a new packing, placement and routing tool for FPGA research, International Workshop on Field Programmable Logic and Application, FPL 97, 1997. ,
DOI : 10.1007/3-540-63465-7_226
Fast prototyping of reconfigurable architectures from a C program, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03., pp.25-28, 2003. ,
DOI : 10.1109/ISCAS.2003.1206381
Exploration Architectural au Niveau Comportemental -Application aux FPGA, 2002. ,
FPGA Resource and Timing Estimation from Matlab Execution Traces, International Symposium on Hardware/Software CoDesign, CODES 02, 2002. ,
A Self-reconfiguration Platform, proceeding of 13 th International Conference on Field-Programmable Logic and Applications, FPL'03, 2003. ,
Dynamically Configurable Security for SRAM FPGA Bitstreams, pp.26-43, 2004. ,
Communication Costs Driven Design Space Exploration for Reconfigurable Architectures, the 13 th International Conference Field Programmable Logic and Applications, FPL'03, 2003. ,
DOI : 10.1007/978-3-540-45234-8_89
Fast Design Space exploration Method for Reconfigurable Architectures, Proceedings of International Conference of Engineering of Reconfigurable Systems and Algorithms, ERSA'03, 2003. ,
Targeting Tiled Architectures in Design Exploration, 10th Reconfigurable Architectures Workshop, RAW03, Workshop of IPDPS 03, 2003. ,
A Modeling Method for Reconfigurable Architectures, IEEE International Workshop on System-on- Chip for Real-Time Applications, IWSOC'02, 2002. ,
DOI : 10.1007/978-1-4615-0351-4_16
Reconfigurable Architecture Modeling. The THF Model, Application to the aSoC Architecture, 2002. ,
Exploration de l'espace de conception de l'architecture des circuits intégrés, ou comment construire une ville nouvelle, 2002. ,
Modélisation d'architectures reconfigurables embarquées, 2001. ,
Dynamically parameterized algorithms and architectures to exploit signal variations for improved performance and reduced power, 2001 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.01CH37221), 2001. ,
DOI : 10.1109/ICASSP.2001.941061
Dynamically Parameterized Architecture for Power-Aware Video Coding Motion Estimation and DCT, Second USF International Workshop on Digital Computational Video, DCV 01, 2001. ,
Survey of Nanoscale Digital System Technology, IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM O2, 2002. ,
Statistical design space exploration for application-specific unit synthesis, Proceedings of the 38th conference on Design automation , DAC '01, pp.641-646, 2001. ,
DOI : 10.1145/378239.379039
Reconfigurable Architecture for WLAN Application, 2003. ,
Domain-Specific Modeling for Rapid System-Level Energy Estimation of Reconfigurable Architectures, Proceedings of International Conference of Engineering of Reconfigurable Systems and Algorithms, ERSA 02, 2002. ,
The design of a SRAM-based field-programmable gate array-Part II: Circuit design and layout, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.7, issue.3, 1999. ,
DOI : 10.1109/92.784093
The Design of an SRAM-Based Field-Programmable Gate Array -Part II: Architecture, IEEE Transactions on VLSI Systems, vol.7, issue.3, 1999. ,
Architecture of cluster-based FPGAs with memory, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044), 2000. ,
DOI : 10.1109/CICC.2000.852633
Programming Architectures For Run-Time Reconfigurable Systems, 1999. ,
A Compartive Study of Performances of the AES Final Candidates Using FPGA, Workshop on Cryptographic Hardware and Embedded Systems, 2000. ,
Architecture reconfigurable dynamiquement pour applications mobiles, 2003. ,
Balancing Interconnect and Computation in a Reconfigurable Computing Array (or, why you dont't really want 100% LUT utilization), Proceedings of the International Symposium of Field Programmable Gate Array, pp.125-134, 1999. ,
Software Radio and Dynamic Reconfiguration on a DSP/FPGA platform. For Publication in Special Issue of Software Radio, Frequenz, Journal of Telecommunications, 2004. ,
Systèmes Radio Dynamiquement Reconfigurables sur des Architectures Hétérogènes, 2003. ,
La rémanence des architectures reconfigurables dynamiquement, 7 ème SYMPosium en Architectures nouvelles de machines, SYMPA'7, pp.23-32, 2001. ,
RaPiD ??? Reconfigurable pipelined datapath, International Workshop on Field Programmable Logic and Applications, FPL'96, 1996. ,
DOI : 10.1007/3-540-61730-2_13
An FPGA Implementation and Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists, proceeding of the third Advanced Encryption Standard candidate conference, AES3, 2000. ,
Caractérisation et modélisation de la consommation de puissance des mémoires sur FPGA, 2003. ,
High-Level Area and Performance Estimation of Hardware Building Blocks on FPGAs, Field-Programmable Logic and Applications Forum on Design Language, 2000. ,
DOI : 10.1007/3-540-44614-1_57
Describing instruction set processors using nML, Proceedings the European Design and Test Conference. ED&TC 1995, pp.503-507, 1995. ,
DOI : 10.1109/EDTC.1995.470354
Comparison of the Hardware Performance of the AES Candidates Using Reconfigurable Hardware, proceeding of the third Advanced Encryption Standard candidate conference, 2000. ,
Estimation et optimisation de la consommation de puissance des circuits logiques programmables du type FPGA, Ecole Nationale Supérieure des Télécommunications, 2000. ,
Power Modelling in Field Programmable Gate Arrays (FPGA), Proceeding of the 9th International Workshop on Field Programmable Logic and Applications, 1999. ,
DOI : 10.1007/978-3-540-48302-1_44
The design of a low energy FPGA, Proceedings of the 1999 international symposium on Low power electronics and design , ISLPED '99, pp.188-193, 1999. ,
DOI : 10.1145/313817.313920
Outils génériques pour le reconfigurable : Application à deux architectures commerciales. RenPar'15, 2003. ,
Methods for evaluating and covering the design space during early design development, Integration, the VLSI Journal, vol.38, issue.2, 2003. ,
DOI : 10.1016/S0167-9260(04)00032-X
ISDL, Proceedings of the 34th annual conference on Design automation conference , DAC '97, 1997. ,
DOI : 10.1145/266021.266108
Are we Realy Ready for the Breakthrough, 10th Reconfigurable Architectures Workshop, RAW 03, Workshop of IPDPS 03, 2003. ,
A decade of reconfigurable computing: a visionary retrospective, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001, pp.13-16, 2001. ,
DOI : 10.1109/DATE.2001.915091
KressArray Xplorer: a new CAD environment to optimize reconfigurable datapath array architectures, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106), 2000. ,
DOI : 10.1109/ASPDAC.2000.835089
A Datapath Synthesis System for the Reconfigurable Datapath Architecture, Asia and South Pacific Design Automation Conference, ASP-DAC 95, 1995. ,
The Future of Reconfigurable Systems, 5th Canadian Conference on Field Programmable Devices, 1999. ,
The Chimarea Reconfigurable Functional Unit, Proceeding of the IEEE symposium on FPGAs for Custom Computing Machines, FCCM 97, pp.87-96, 1997. ,
Accelerating Design Space Exploration, Proceedins of 5 th IEEE International Conference on ASIC, 2003. ,
Augmenting a Microprocessor with Reconfigurable Hardware, 2000. ,
Garp: a MIPS processor with a reconfigurable coprocessor, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186), 1997. ,
DOI : 10.1109/FPGA.1997.624600
Design techniques for low-power systems, Journal of Systems Architecture, vol.46, issue.1, 2000. ,
DOI : 10.1016/S1383-7621(98)00057-5
Java as a specification language for hardware-software systems, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97, pp.690-697, 1997. ,
DOI : 10.1109/ICCAD.1997.643613
Mapping of DSP Algorithms on Field Programmable Function Arrays, International Workshop of Field Programmable Logic and Application, FPL 00, 2000. ,
DOI : 10.1007/3-540-44614-1_43
Multilanguage Specification for System Design and CoDesign. Chapter in « System-Level Synthesis », NATO ASI, 1998. ,
Fuzzy Expert Systems, 1992. ,
PICO: automatically designing custom computers, IEEE Computer, pp.39-47, 2002. ,
DOI : 10.1109/MC.2002.1033026
Architecture reconfigurable méthodologie et modélisation VHDL pour la mise au point d'applications, ème Symposium en Architectures Nouvelles de Machines, SympA'6, pp.19-22, 2000. ,
An approach for quantitative analysis of application-specific dataflow architectures, Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2003. ,
DOI : 10.1109/ASAP.1997.606839
A Fast Reconfigurable ALU for Xputers, 1996. ,
A Datapath Synthesis System for the Reconfigurable Datapath Architecture, Asia and South Pacific Design Conference, Asp-DAC 95, pp.29-30, 1995. ,
Low-Energy Embedded FPGA Structures, Proceeding of the International symposium on Low Power Electronics and Design, pp.155-160, 1998. ,
Fast area estimation to support compiler optimizations in FPGA-based reconfigurable systems, Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2002. ,
DOI : 10.1109/FPGA.2002.1106678
Adaptative System on a Chip (aSoc) : A Backbone for Power-Aware Signal Processing Cores, IEEE International Conference on Image Processing, ICIP 03, 2003. ,
Power-Aware System on a Chip, Boston Area Architecture Workshop, 2003. ,
Adaptative System on a Chip (aSoc) for Low-Power Signal Processing, Thirty-Fith Asilomar Conference on Signals, and Computers, 2001. ,
Abstraction, modélisation et outils de CAO pour les circuits intégrés reconfigurables, 2000. ,
Outils génériques pour les architectures reconfigurables, 7ème Symposium sur les Architectures nouvelles de machines (SympA'7), 2001. ,
Evaluation of the Traffic-Performance Characteristics of System_onChip Communication Architectures, International Conference on VLSI Design, VLSI 01, pp.21-35, 2001. ,
Performance analysis of systems with multi-channel communication architectures, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design, pp.530-537, 2000. ,
DOI : 10.1109/ICVD.2000.812662
Efficient Exploration of the SoC Communication Architecture Design Space, International Conference on Computer Aided Design, ICCAD 00, pp.424-430, 2000. ,
An Algorithm for Path Connections and its Applications, IRE Transactions on Electronic Computers, vol.10, pp.346-365, 1961. ,
Aide à la conception des systèmes sur puce hétérogène par l'exploration paramétrable des solutions au niveau système, 2003. ,
Multigranularity Metrics for the Era of Strongly Personalized SoCs, Design Automation and Test in Europe, 2003. ,
Design Trotter : Building and Selecting Architectures for Embedded Multimedia Applications, IEEE International Symposium on Consumer Electronics, ISCE 03, 2003. ,
Estimation du parallélisme au niveau système pour l'exploration de l'espace de conception de systèmes enfouis, Technique et Science Informatiques, RSTI-TSI, vol.22, pp.315-349, 2003. ,
Using edif2blif Version 1.0 An Architecture for Saclable On-Chip Communication, 1998. ,
aSoC : A Saclable, Single-Chip Communications Architecture, the IEEE International. Conference on Parallel Architectures and Compilation Technique, 2000. ,
An Extensible, System-On-Programmable-Chip, Content-Aware Internet Firewall, Proceeding of 13 th International Conference on Field-Programmable Logic and Applications, 2003. ,
DOI : 10.1007/978-3-540-45234-8_83
A reconfigurable arithmetic array for multimedia applications, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays , FPGA '99, 1999. ,
DOI : 10.1145/296399.296444
Pathfinder : A Negotiation_based Performance-driven Router for FPGAs, FPGA, pp.111-117, 1995. ,
Production de compilateurs flexibles pour la conception de processeurs programmables spécialisés, 1999. ,
MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines FPGA-96, 1996. ,
DOI : 10.1109/FPGA.1996.564808
REMARC (abstract), Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays , FPGA '98, 1998. ,
DOI : 10.1145/275107.275164
Rapid Design Space Exploration of Heterogeneous Embedded Systems using Symbolic Search and ,
Exploring optimal cost-performance designs for Raw microprocessors, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251), 1998. ,
DOI : 10.1109/FPGA.1998.707877
Power: a first-class architectural design constraint, Computer, vol.34, issue.4, pp.52-57, 2001. ,
DOI : 10.1109/2.917539
Coarse-Grained Reconfigurable Architecture Design Space Architecture Exploration, 2001. ,
Accurate area and delay estimators for FPGAs, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition, 2002. ,
DOI : 10.1109/DATE.2002.998400
Cours d'Economie Politique. F. Rouge, Lausanne, 1896 Retargeting of Compiled Simulators for Digital Signal Processors Using a Machine Description Langage, Design, Automation and Test in Europe Confrence, DATE 00, pp.669-938, 2000. ,
Exploring embedded-systems architectures with Artemis, IEEE Computer, pp.57-63, 2001. ,
DOI : 10.1109/2.963445
A Flexible Power Model for FPGAs, Proceeding of the 12th International Conference on Field-Programmable Logic and Applications, 2002. ,
DOI : 10.1007/3-540-46117-5_33
Power Estimation for Field Programmable Gate Arrays, 1999. ,
Silicon Platforms for the Next Generation Wireless Systems -What Role does Reconfigurable Hardware Play ? In International Workshop of Field Programmable Logic and Application, p.0, 2000. ,
A Survey of Reconfigurable Computing Architectures, LCNS 1482, pp.376-385, 1998. ,
The Lost History of the Transistor, IEEE Spectrum, pp.36-41, 2004. ,
Caractérisation de l'impact du routage sur les performances (vitesse et consommation de puissance) d'un FPGA, 2003. ,
Re-Configurable Computing in Wirless, 38th Design Automation Conference, 2001. ,
Architectures Reconfigurables Dynamiquement pour les Systèmes Embarqués, GRESTI'01, 2001. ,
Architectures Reconfigurables Dynamiquement pour les Systèmes sur Puce, 2002. ,
Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications, IEEE Design Automation and Test in Europe, DATE 02, pp.553-557, 2002. ,
A Quick Safari Through the Reconfigurable Jungle, 38 th DAC, 2001. ,
FIPSOC Mixed Signal System-on-Chip, 2002. ,
MorphoSys, Proceedings of the 37th conference on Design automation , DAC '00, pp.465-481, 2000. ,
DOI : 10.1145/337292.337583
Dynamic Power in Virtex TM -II FPGA Family, ACM/SIGDA Symposium of Field Programmable Gate Arrays, FPGA'02, 2002. ,
Using Estimates from Behavioral Synthesis Tools in Compiler-Directed Design Spcae Exploration, 40 th Design Automation Conference, DAC 03, 2003. ,
A Compliler Approach to Fasst Hardware Deigsn Space Exploration in FPGA-based Systems, Proceeding of the ACM Conference on Programming Language Deisgn and Implementation, 2002. ,
PulseDSP : Synthesisable DSP Co-processor, 2000. ,
Reconfigurable Computing for Digital Signal Processing : A Survey, The Journal of VLSI Signal Processing, vol.28, issue.1/2, pp.7-27, 2001. ,
DOI : 10.1023/A:1008155020711
The Rise of Reconfigurable Systems In proceeding of Engineering of Reconfigurable Systems and Application, ERSA 03, 2003. ,
An FPGA Run-Time System for Dynamical On-Demand Reconfiguration, pp.26-43, 2004. ,
ALFA fine grain dataflow machine, International Programming, M.A. Orgun and E.A. Ashcroft edition, 1996. ,
Baring it all to software: Raw machines, Computer, vol.30, issue.9, pp.86-93, 1997. ,
DOI : 10.1109/2.612254
A Comparison of the AES Candidates Amenability to FPGA Implementation In proceeding of the third Advanced Encryption Standard candidate conference, AES3, 2000. ,
How Secure Are FPGAs in Cryptographic Applications?, proceeding of 13 th International Conference on Field-Programmable Logic and Applications, FPL 03, 2003. ,
DOI : 10.1007/978-3-540-45234-8_10
Architectures and Algorithms for Field Programmable Gate Arrays with Embedded Memory, Canada, 1997. ,
The Memory/Logic Interface in FPGA's With Large Embedded Memory Arrays, IEEE Transactions on VLSI Systems, vol.7, issue.1, 1999. ,
One Chip : An FPGA Processor with Reconfigurable Logic, Proceedings of the IEEE Symposium on FPGA for Custom Computing Machines, FCCM 96, pp.126-135, 1996. ,
Virtex-II Pro Platform FPGAs, 2004. ,
Software Manual and Documentation for ISE6.1i Technical Document, 2004. ,
Revolutionary for the Next Generation Platform FPGAs, 2003. ,
Virtex-II Platform FPGAs, 2003. ,
How to Choose the Grain Size of a Parallel Computer, 1994. ,
Interconnect Architecture Exploration for Low-Energy Reconfigurable Single-Chip DSPs, IEEE Computer Society Workshop on VLSI, 1999. ,
Laura : Leiden Architecture Research and Exploration Tool, the 13 th International Conference Field Programmable Logic and Applications, FPL'03, 2003. ,
From High Level Application Specification to System-Level Architecture, Definition: Exploration, Design and Compilation, Proceeding of the International Workshop on Compilers for Parallel Computers, CPC 03, pp.39-49, 2003. ,