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Theses
Méthode de validation globale pour les systèmes monopuces
Méthode de validation globale pour les systèmes monopuces
Abstract : Actual technologies facilitate integration of many components onto a single chip. These systems called system on chip (SoC) are a heterogeneous assembly of hardware and software components. As quality and time to market constraints of SoCs increase, validation becomes the key point (70% of the overall design process). Verification of the integration is done through simulation and consists to check component functionalities and interconnections in the system. It is often achieved by executing software programs on the embedded processors. Programs are generally designed at low level (assembly, C) which makes difficult to design complex test scenarios that need sophisticated synchronisation schemes. Furthermore, their use does not enable performing the complete system validation. The main contributions of this work for accelerating validation are: (1) the definition of a validation methodology using different verification techniques targeting specific SoC issues; (2) the definition of a new verification method of the integration based on high level software test programs using an operating system. This method was validated on an industrial SoC aimed at high definition television applications.
Keywords :
system-on-chip design and validation
https://tel.archives-ouvertes.fr/tel-00012051
Contributor : Lucie Torella <>
Submitted on : Tuesday, March 28, 2006 - 3:30:48 PM
Last modification on : Friday, December 11, 2020 - 8:28:04 AM
Long-term archiving on: : Saturday, April 3, 2010 - 11:03:29 PM
Contributor : Lucie Torella <>
Submitted on : Tuesday, March 28, 2006 - 3:30:48 PM
Last modification on : Friday, December 11, 2020 - 8:28:04 AM
Long-term archiving on: : Saturday, April 3, 2010 - 11:03:29 PM