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Conception Automatique de Chemins de Données en Logique Asynchrone QDI

Abstract : In recent years, asynchronous circuits have become a natural solution for synchronous circuit design problems related to the use of submicron technologies. By using a local synchronization mechanism instead of a global clock, asynchronous circuits are more reliable, robust and modular than their equivalent synchronous form. Additionally, by not using a global clock, design constrains such as low-power consumption, low noise and security may be addressed. However, the ever-increasing interest in asynchronous circuits faces an important drawback, which is the lack of methods and tools that help designing such circuits.
In this context, this thesis focuses on designing QDI (quasi-delay insensitive) asynchronous data paths. Initially, this thesis proposes and evaluates a method for comparing different asynchronous circuit implementations. Next, the two main arithmetic operators, which consist in adders and multipliers, are studied. In this study, not only several architectures were evaluated but also the impact of different data coding was analyzed. The comparison method and the arithmetic operator generation were automated, allowing designers to choose an implementation, which fits best the design constraints.
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Submitted on : Tuesday, January 10, 2006 - 7:35:40 AM
Last modification on : Friday, December 11, 2020 - 8:28:04 AM
Long-term archiving on: : Saturday, April 3, 2010 - 9:03:23 PM


  • HAL Id : tel-00011332, version 1




J. Fragoso. Conception Automatique de Chemins de Données en Logique Asynchrone QDI. Micro et nanotechnologies/Microélectronique. Institut National Polytechnique de Grenoble - INPG, 2005. Français. ⟨tel-00011332⟩



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