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Conception de circuits MMIC BiMOS SiGe appliqués à la synthèse de fréquence fractionnaire

Abstract : Circuit integration is a key factor for size and cost reduction of communication systems. Transceiver systems need the local oscillator for the transposition of the modulated signal to an intermediate frequency or to the base band frequency. This local oscillator is usually realized with a phase locked loop (PLL). The aim of this study is to design a completely integrated fractional PLL in the X band frequency range (8 GHz-12 GHz) in BiCMOS technology. Firstly, an integrated integer PLL is presented, with the specifications and design means. The PLL's basic blocks are described and the influence of each of these blocks on the PLL phase noise specification is evaluated. This study gives a performance assessment carrying out dynamic and noise performances of the voltage controlled oscillator (VCO). The study and design of the voltage controlled oscillator are the subjects of the second chapter. Its fundamental principles and design concerns in monolithic design are presented. Circuit performances evaluation is of prime importance in monolithic design, especially for phase noise prediction. The design of two different VCO topologies is presented (a parallel topology and a serial topology). The design methodology is based on the minimization of the base emitter current noise source conversion into phase noise, leading to the optimum bias condition for a low phase noise voltage controlled oscillator. On the assumption of the preponderance of the base emitter current noise conversion in the phase noise generation, we propose a hybrid bias solution using a short circuit to reduce this current noise: this is implemented on the serial VCO. Another design based on the push-push topology is realized for a 20 GHz VCO. The phase noise performance for this design defines the state of the art for this technology and this oscillation frequency. Finally, in the last chapter, the fractional division is studied: the existing solutions are given and the implemented solution is describe d. The completely integrated PLL is implemented, and the total phase noise is estimated, carrying out the contribution of the integrated loop filter which is a major concern in integrated PLL.
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Contributor : Emilie Marchand <>
Submitted on : Tuesday, November 22, 2005 - 2:00:18 PM
Last modification on : Friday, January 10, 2020 - 9:08:09 PM
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  • HAL Id : tel-00011081, version 1


Wa Wong. Conception de circuits MMIC BiMOS SiGe appliqués à la synthèse de fréquence fractionnaire. Micro et nanotechnologies/Microélectronique. Université Paul Sabatier - Toulouse III, 2003. Français. ⟨tel-00011081⟩



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