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Génération Automatique de Modèles de Simulation pour la Validation de Systèmes Hétérogènes Embarqués

Abstract : As quality and time-to-market constraints of systems-on-chip increase, validation becomes the key point of the design process. Validation represents more than 50% of design time. The ever-increasing heterogeneity of systems-on-chip makes validation harder. This heterogeneity concerns different aspects of the system such as: abstraction levels, API's and communication protocols, specification languages, etc. The key points to reduce validation time are : (1) mastering heterogeneous components integration by adapting their communication (2) and generating simulation models automatically.
The main contributions of this work for accelerating validation time are : (1) the definition of a service-based model for communication adapters in order to enable the cosimulation of heterogeneous systems-on-chip ; (2) the definition and implementation of an automatic generation flow of simulation models for heterogeneous systems-on-chip.
The proposed approach was validated on two systems-on-chip : a VDSL modem and a MPEG-4 encoder.
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https://tel.archives-ouvertes.fr/tel-00010903
Contributor : Lucie Torella <>
Submitted on : Tuesday, November 8, 2005 - 10:36:45 AM
Last modification on : Friday, December 11, 2020 - 8:28:04 AM
Long-term archiving on: : Friday, April 2, 2010 - 10:53:34 PM

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  • HAL Id : tel-00010903, version 1

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Citation

A. Sarmento. Génération Automatique de Modèles de Simulation pour la Validation de Systèmes Hétérogènes Embarqués. Micro et nanotechnologies/Microélectronique. Université Joseph-Fourier - Grenoble I, 2005. Français. ⟨tel-00010903⟩

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