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Exploration des liens entre la synthèse de haut niveau (HLS) et la synthèse au niveau transferts de registres (RTL)

Abstract : The microelectronics industry has been undergoing a pace of change in order to cope with the increasing complexity of VLSI. This thesis work addresses the subject of linking High Level Synthesis (HLS) of VLSI with the Register Transfer Level (RTL) synthesis prevailing to be the current Industrial practice. Starting from the HLS results, we generate quality RTL specifications equivalent of the initial behavioral specification. The generated results aim at an improved flexiblity, efficiency and parameterization from a designer's view point in terms of the final architecture. A HLS starts from a behavioral description in a Hardware Description Language (HDL) such as the VHDL, performs a certain NP-complete steps such as scheduling, allocation to generate a RTL architecture based on a controller and a datapath. Both controller and datapath can be synthesized by the logic synthesis tools to realize an Application Specific Integrated Circuit (ASIC) or a Field Programmable Gate Array (FPGA). However, for efficieny reasons, it is preferable to synthesize the datapath using a datapath compiler. Further, the architecture obtained as a result of HLS can be parameterized. We begin by developing a method called a Personalization to yield a flexible RTL architecture. This method allows the designers not only to add the information related to the synchronization, but also to mix in a high level description, both synthesizable and un synthesizable parts. Next we define a method known as a Decomposition. It allows to transform an available HLS datapath into an interconnection of several regular datapaths and a glue logic. All the extracted regular datapaths can undergo efficient synthesis by a datapath compiler. Finally, we present the delivery of generic datapaths supporting parameterizable architectures at the RT level. The idea is incorporated into a VHDL translator from the intermediate data structure used by AMICAL, a HLS tool.
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Submitted on : Wednesday, October 26, 2005 - 8:57:48 AM
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  • HAL Id : tel-00010764, version 1




V. Vijayaraghavan. Exploration des liens entre la synthèse de haut niveau (HLS) et la synthèse au niveau transferts de registres (RTL). Micro et nanotechnologies/Microélectronique. Institut National Polytechnique de Grenoble - INPG, 1996. Français. ⟨tel-00010764⟩



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