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Theses

Le test unifié de cartes appliqué à la conception de systèmes fiables

Abstract : On one hand, if the goal is to ensure that the design validation, the manufacturing and the maintenance testing, along with the concurrent error detection are efficiently performed in electronic systems, one is led to integrate the off-line and the on-line testing into circuits. Then, for complex systems to make profit of these two types of tests, such unification must be extended from the circuit to the board and module levels. On the other hand, although the unification of off-line and on-line testing techniques makes possible the design of systems suiting any safety application, the hardware added for increasing the application safety also decreases the system availability and reliability, since the probability of occurrence of faults increases. Faced to these two antagonist aspects, this thesis aims at finding a compromise between the safety and the reliability of complex electronic systems. Thus, firstly we propose a solution to the off-line test and diagnosis problems found in the intermediate steps in the evolution towards boards which are 100% compliant with the IEEE standard for boundary scan testing. An approach for the BIST (Built-In Self-Test) of boundary scan circuits and interconnects then illustrates the ultimate step in the board off-line testing. Next, the UBIST (Unified BIST) scheme - merging BIST and self-checking capabilities for circuit on-line testing, is combined with the IEEE standard for boundary scan testing, in order to obtain a design strategy for unifying the tests of interconnects and circuits populating boards and modules. Finally, we propose a fault-tolerant scheme based on the duplication of these kind of modules which ensures the competitivity of the resulting system in terms of reliability at the same time as preserving the inherent module safety.
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Submitted on : Wednesday, October 26, 2005 - 8:11:26 AM
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  • HAL Id : tel-00010759, version 1

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Marcelo Lubaszewski. Le test unifié de cartes appliqué à la conception de systèmes fiables. Micro et nanotechnologies/Microélectronique. Institut National Polytechnique de Grenoble - INPG, 1994. Français. ⟨tel-00010759⟩

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