Abstract : This thesis presents a contribution to the domain of silicon compilation. It deals with the integration of an architectural synthesis tool within the existing CAD environments. The main issue is the personalization of the abstract architecture resulting from the high-level synthesis, in order to generate descriptions which are compatible with the existing RTL simulation and synthesis tools. The goal is to provide several architectural models using different synchronization schemes in order to meet different application needs. After the introduction of the architectural synthesis tool AMICAL and several RTL architectural models, this thesis presents a method and a tool for the personalization of the abstract architecture generated by AMICAL, and the translation of the resulting SOLAR files into their VHDL equivalents. Finally, a comparative study of the different architectural models using several exemples is detailed. This study indicates that we need several architectural models for different applications. These architectural models differ in the structure, the macro-component library and the synchronization model used.