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Application des technologies CMOS sur SOI aux fonctions d'interface des liens de communication haut débit (> 10 Gbit/s)

Abstract : The purpose of this work is to investigate the advantages of a CMOS/SOI partially depleted 0.13µm technology for the design of high data rate communications circuits. This work has been focused on the Clock and Data Recovery function (CDR), with an in depth analysis of the VCO. A roadmap has been established to investigate the different technological choices in SOI technology (active and passive components). Nine circuits (VCO and oscillators) at 10GHz have been designed and processed to select the best ones. Measured performances show the interest in using CMOS/SOI for high frequency range. Then, targeting 40Gbit/s applications, we designed and processed a 4x10GHz multi-phases VCO. Experimental results demonstrate a significant improvement of the figure of merit when comparing this SOI design to previously published results.
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https://tel.archives-ouvertes.fr/tel-00010675
Contributor : David Axelrad <>
Submitted on : Tuesday, October 18, 2005 - 4:23:51 PM
Last modification on : Thursday, June 11, 2020 - 5:04:05 PM
Long-term archiving on: : Friday, April 2, 2010 - 10:15:13 PM

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  • HAL Id : tel-00010675, version 1

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David Axelrad. Application des technologies CMOS sur SOI aux fonctions d'interface des liens de communication haut débit (> 10 Gbit/s). Réseaux et télécommunications [cs.NI]. Institut National Polytechnique de Grenoble - INPG, 2005. Français. ⟨tel-00010675⟩

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