Abstract : This thesis is inserted in the research project on «Vision System by Silicon Retina ». The research work of this thesis is focused on the design and realisation of a CMOS logarithmic imager with an onchip
FPN (Fixed Pattern Noise) compensation in standard CMOS technology. Recent experiences
have shown that an image sensor with logarithmic response, similar to that of human eyes, is very
adapted to vision applications. This logarithmic response gives not only an image signal proportional
to the optical contrast but also a wide dynamic range thanks to the logarithmic compression.
One of the most critical problems is the FPN from a logarithmic pixel array, which reduces the quality
of image and limits its utility in real applications. In this thesis, we have explored a structure radically
different from these used by many other researchers: using a photodiode working in solar cell mode
rather than in photoconductor mode. Besides this photodiode is combined with a reset transistor which
permits the generation of dark reference signal under illumination conditions. This new approach
opens the way to an easy and effective on-chip compensation of FPN.
This photoreceptor has been intensively studied in this thesis and a 160x120-pixel prototype chip has
been designed and fabricated in 0.8µm CMOS technology via French CMP service. This prototype
chip has been fully tested and characterised. The results of this experimentation has not only validated
the theoretical predictions but also demonstrated a good image quality and a high sensitivity. Some
design and electrical problems and phenomena in this sensor chip have been also investigated in this
thesis and the solutions to these problems could be interesting to designers and researchers in this area.
At the end some open questions on the logarithmic imager have been underlined and correspondent
research directions have been pointed out.