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Circuits Reconfigurables Robustes

Abstract : This thesis is devoted to the development of Single Event Upset hardness methodologies dedicated to SRAM based FPGA. SEU may alter the FPGA function through induced errors in the configuration memory. This is the major concern about the use of FPGA in radiation environment. Furthermore they affect the user logic in a similar way than classical integrated circuits.
Thanks to restructuration of their transistors arrangement and number, we propose a new inverter and data latch architectures. It allows us to define an SEU proof architecture for user logic hardness. This method is although applicable to harden the configuration memory. However it is area consuming.
So we propose a second methodology dedicated to the configuration memory. It is an Error Correction And Detection algorithm based on parity testing.
Finally we present the test circuit we designed to validate the restructurating approach.
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Contributor : Jean-Max Dutertre <>
Submitted on : Wednesday, September 28, 2005 - 7:07:12 PM
Last modification on : Monday, January 7, 2019 - 2:12:05 PM
Long-term archiving on: : Friday, April 2, 2010 - 10:31:21 PM


  • HAL Id : tel-00010317, version 1



Jean-Max Dutertre. Circuits Reconfigurables Robustes. Micro et nanotechnologies/Microélectronique. Université Montpellier II - Sciences et Techniques du Languedoc, 2002. Français. ⟨tel-00010317⟩



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