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SIMULATION SYMBOLIQUE DES CIRCUITS DÉCRITS AU NIVEAU ALGORITHMIQUE

Abstract : This PhD thesis presents a new symbolic simulation method for circuits described at algorithmic level. First the VHDL description is modeled as a set of recurrence equations (SRE) that describe the state of the system at a given time as a function of previous states. After an automatic extraction of the model SRE, the VHDL simulation algorithm is applied for a fixed number of simulation cycles given by the designer. During the simulation, a test scenario and a simplification via substitution rules are applied to compute the symbolic or the numeric expression of each object in the design (register, signal or output port). Three test modes are defined and explained: tracking, reasoning and mixed. They are based on separation of the operative part from the control part of the circuit. The symbolic simulator and the VHDL to SRE compiler are implemented using Mathematica.
A verification methodology around the SRE symbolic simulation is proposed. Multiple verification paradigms (pattern matching, theorem proving and SAT) are applied to the symbolic simulation results to validate or to prove the properties of the circuit. The methodology is illustrated on two real size circuits (a RAM memory and digital filter) and on several academic examples.
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https://tel.archives-ouvertes.fr/tel-00009776
Contributor : Lucie Torella <>
Submitted on : Tuesday, July 19, 2005 - 12:50:09 PM
Last modification on : Friday, December 11, 2020 - 8:28:04 AM
Long-term archiving on: : Friday, April 2, 2010 - 10:44:25 PM

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  • HAL Id : tel-00009776, version 1

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Citation

G. Al-Sammane. SIMULATION SYMBOLIQUE DES CIRCUITS DÉCRITS AU NIVEAU ALGORITHMIQUE. Micro et nanotechnologies/Microélectronique. Université Joseph-Fourier - Grenoble I, 2005. Français. ⟨tel-00009776⟩

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