A. Après-initialisation-des-registres, C. , and L. Valeur, 0250 a été chargée dans le pointeur de pile (LDS #$0250), la valeur $21 dans le CCR (LDAA #$21 et TAP)

. La-première-ligne, erreur initiale à corriger et les deux dernières lignes montrent la concordance des résultats entre la version originale et la version corrigée du code source sauf en ce qui concerne le registre X qui n'est pas initialisé de la même façon dans les deux versions. Le premier octet de chaque ligne représente le CCR et permet de constater que les bits S et X sont bien corrigés (les 2 bits de poids fort sont égaux à 1) et que l'instruction DAA modifie à présent

A. Après-l-'initialisation-des-registres, C. , and L. Valeur, 0500 est chargée dans le pointeur de pile (LDS #$0500), la valeur $1000 dans le registre X (LDX #$1000) et la valeur $50 est chargée à l'adresse $1049 par l'intermédiaire de l'accumulateur A (LDAA #$50, STAA $49,X) avant d'exécuter la séquence d'instructions NEG (NEG $49,X) suivie de SWI. Les résultats comparatifs de ces tests sont les suivants: ancienne version

E. Références, J. Acuna, A. Dervenis, F. Pagones, R. Yang et al., Simulation Techniques for Mixed Analog and Digital Circuits, IEEE Journal of Solid-State Circuits, vol.25

L. Alexandrescu, M. Anghel, and . Nicolaidis, Simulating Single Event Transients in VDSM ICs for Ground Level Radiation, Journal of Electronic Testing, vol.20, issue.4, 2002.
DOI : 10.1023/B:JETT.0000039608.48856.33

URL : https://hal.archives-ouvertes.fr/hal-00013725

L. Alexandrescu, M. Anghel, and . Nicolaidis, New methods for evaluating the impact of single event transients in VDSM ICs, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings., pp.99-107, 2002.
DOI : 10.1109/DFTVS.2002.1173506

URL : https://hal.archives-ouvertes.fr/hal-00013736

M. Allenspach, SEGR in power MOSFET: prediction of breakdown biases and evaluation of oxide thickness dependence, NS-42, N°6, décembre 1995, pp.1922-1927

M. Allenspach, C. Dachs, and G. H. Johnson, SEGR and SEB in n-channel power MOSFETs, IEEE Transactions on Nuclear Science, vol.43, issue.6, p.43, 1996.
DOI : 10.1109/23.556887

L. Anghel, R. Velazco, S. Saleh, S. Deswaertes, and A. Elmoucary, Preliminary validation of an approach dealing with processor obsolescence, Proceedings. 16th IEEE Symposium on Computer Arithmetic, 2003.
DOI : 10.1109/DFTVS.2003.1250148

URL : https://hal.archives-ouvertes.fr/hal-00005829

J. A. Barth, Space Environments and Testing, Single Events Effects Symposium, 2000.

J. Barth, Modeling Space Radiation Environments, IEEE NSREC short course, 1997.

J. Barth, Military and Aerospace Applications of Programmable Devices and Technologies, Conference, Radiation Environments, 1998.

R. Baumann, T. Hossain, S. Murata, and H. Kitagawa, Boron compounds as a dominant source of alpha particles in semiconductor devices, 33rd IEEE International Reliability Physics Symposium, p.297, 1995.
DOI : 10.1109/RELPHY.1995.513695

R. Baumann, T. Hossain, E. Smith, H. Murata, and . Kitagawa, Boron as a primary source of radiation in high density DRAMs, 1995 Symposium on VLSI Technology. Digest of Technical Papers, pp.81-82, 1995.
DOI : 10.1109/VLSIT.1995.520868

M. P. Baze and S. P. Buchner, Attenuation of single event induced pulses in CMOS combinational logic, IEEE Transactions on Nuclear Science, vol.44, issue.6, pp.2217-2223, 1997.
DOI : 10.1109/23.659038

F. Bezzerra, S. Barde, J. L. Carayon, M. Sarthou, and S. Borkar, Nanocontrollers characterization under radiation, 1999 Fifth European Conference on Radiation and Its Effects on Components and Systems. RADECS 99 (Cat. No.99TH8471), pp.338-342, 1999.
DOI : 10.1109/RADECS.1999.858653

]. J. Boud and . Boudenot, Tenue des circuits aux radiations ionisantes

S. Buchner, M. Base, D. Brown, D. Mcmorrow, and J. Melinger, Comparison of error rates in combinational and sequential logic, IEEE Transactions on Nuclear Science, vol.44, issue.6, pp.2209-2216, 1997.
DOI : 10.1109/23.659037

H. Cha and J. H. Patel, A logic-level model for ??-particle hits in CMOS circuits, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93, pp.538-542, 1993.
DOI : 10.1109/ICCD.1993.393319

G. Choi, R. Iyer, and R. Saleh, A Fault Behavior Model for an Avionic Microprocessor: A Case Study, International. Working Conf. on Dependable Computing for Critical Applications, pp.71-77, 1989.
DOI : 10.1007/978-3-7091-9123-1_8

. Cohen, Soft error considerations for deep-submicron CMOS circuit applications, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), pp.315-318, 1999.
DOI : 10.1109/IEDM.1999.824159

. P. Coli-97-]-j and . Colinge, Durcissement des Circuits Intégrés contre les Effets dus aux Rayonnements, Journée Technique, 1997.

I. Micro, Trends and challenges in VLSI circuit reliability, pp.23-37, 2003.

P. E. Dodd, Device simulation of charge collection and single-event upset, IEEE Transactions on Nuclear Science, vol.43, issue.2, pp.561-575, 1996.
DOI : 10.1109/23.490901

P. E. Dodd, F. W. Sexton, and P. S. Winokur, Three-Dimentional simulation of charge collection and multiple-bit upset in Si devices, IEEE Transactions on Nuclear Science, vol.41, pp.62005-2017, 1994.

P. E. Dodd and F. W. Sexton, Critical charge concepts for CMOS SRAMs, IEEE Transactions on Nuclear Science, vol.42, issue.6, pp.1764-1771, 1995.
DOI : 10.1109/23.488777

R. S. Farino and . Flores, Impact of technology trends on SEU in CMOS SRAMs, IEEE Transactions on Nuclear Science, vol.43, issue.6, pp.2797-2804, 1996.

P. E. Dodd, M. R. Shaneyfelt, and F. W. Sexton, Charge collection and SEU from angled ion strikes, IEEE Transactions on Nuclear Science, vol.44, issue.6, pp.2256-2265, 1997.
DOI : 10.1109/23.659044

URL : http://www.osti.gov/scitech/servlets/purl/516010

D. 'hose, J. L. Leray, and P. S. Winokur, Impact of ion energy on single-event upset, IEEE Transactions on Nuclear Science, vol.45, issue.6, pp.2483-2491, 1998.

P. Duba and R. K. Iyer, Transient fault behaviour in a microprocessor: a case study, Proceedings of IEEE International Conference on Computer Design, pp.272-276, 1988.

A. Ghosh and B. W. Johnson, System-level modeling in the ADEPT environment of a distributed computer system for real-time applications, Proceedings of 1995 IEEE International Computer Performance and Dependability Symposium, pp.194-203, 1995.
DOI : 10.1109/IPDS.1995.395832

T. J. O-'gorman, Field testing for cosmic ray soft errors in semiconductor memories, IBM Journal of Research and Development, vol.40, issue.1, pp.41-49, 1996.
DOI : 10.1147/rd.401.0041

C. A. Gossett, Single event phenomena in atmospheric neutron environments, IEEE Transactions on Nuclear Science, vol.40, issue.6, pp.1845-1852, 1993.
DOI : 10.1109/23.273471

. J. Griff-97-]-p and . Griffin, The role of thermal and fission neutrons in reactor neutron-induced upsets in commercial SRAMs, IEEE Transactions on Nuclear Science, vol.44, issue.6, pp.2079-2086, 1997.
DOI : 10.1109/23.659019

C. S. Guenzer, E. A. Wolicki, and R. G. Allas, Single Event Upset of Dynamic Rams by Neutrons and Protons, IEEE Transactions on Nuclear Science, vol.26, issue.6, pp.5048-5052, 1979.
DOI : 10.1109/TNS.1979.4330270

E. Jenn, J. Arlat, M. Rimen, J. Ohlsson, and J. Karlsson, Fault injection into VHDL models: the MEFISTO tool, Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing, pp.66-75, 1994.
DOI : 10.1109/FTCS.1994.315656

K. Johansson, In-flight and ground testing of single event upset sensitivity in static RAMs, IEEE Transactions on Nuclear Science, vol.45, issue.3, pp.1628-1632, 1998.
DOI : 10.1109/23.685251

T. Karnik, P. Hazucha, and J. Patel, Characterization of soft errors caused by single event upsets in CMOS processes, IEEE Transactions on Dependable and Secure Computing, vol.1, issue.2, pp.128-143
DOI : 10.1109/TDSC.2004.14

T. P. Ma and P. Dussendorfer, Ionizing Radiation Effects in Mos Devices and Circuits, 1989.

L. W. Massengill, A. E. Baranski, D. O. Nort, J. Meng, and B. L. Bhuva, Analysis of single-event effects in combinational logic-simulation of the AM2901 bitslice processor, IEEE Transactions on Nuclear Science, vol.47, issue.6, 2000.
DOI : 10.1109/23.903816

L. W. Massengill, M. S. Reza, B. L. Bhuva, and T. L. Turflinger, Single-event upset cross-section modeling in combinational CMOS logic circuit, Journal of Radiation Effects, Research, and Engineering, vol.16, issue.1, 1998.

D. G. Mavis and P. H. Eaton, Soft error rate mitigation techniques for modern microcircuits, 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320), pp.216-225, 2002.
DOI : 10.1109/RELPHY.2002.996639

T. C. May and M. H. Woods, Alpha-particle-induced soft errors in dynamic memories, IEEE Transactions on Electron Devices, vol.26, issue.1, pp.2-9, 1979.
DOI : 10.1109/T-ED.1979.19370

P. J. Mcnulty, P. Roche, J. M. Palau, M. W. Savage, and J. Gasiot, Threshold LET for SEU induced by low energy ions [in CMOS memories], IEEE Transactions on Nuclear Science, vol.46, issue.6, pp.1370-1377, 1999.
DOI : 10.1109/23.819095

. Campbell, Investigations of single-event upsets and charge collection in microelectronics using variable-length laser-generated chage tracks, IEEE Transactions on Nuclear Science, vol.45, 1998.

S. Mitra, N. Seifert, M. Zhang, Q. S. Shi-;-k, and . Kim, Robust System design witn Built_In Soft-Error Resilience, IEEE Design and Test of Computers, vol.38, issue.2, pp.43-52, 2005.
DOI : 10.1109/mc.2005.70

A. Moll and . Rubio, Methodology of detection of spurious signals in VLSI circuits, Proceedings ETC 93 Third European Test Conference, pp.491-496, 1993.
DOI : 10.1109/ETC.1993.246601

. Motorola, 6. Motorola, S. Microcontroller, A. Mukhopadhyay, K. Raychowdhury et al., M68HC11 Reference Manual -Motorola -literature reference M68HC11RM/AD " [Muk-03 Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modelling, Design Automation Conference, 2003. Proceedings, pp.2-6, 2003.

. Musse-91-]-o and . Musseau, Effets des Ions Lourds Energétiques sur les Circuits Intégrés Application au cas de Circuits MOS, MOS sur Isolants et GaAs, Thèse, 1991.

. Norm-96a-]-e and . Normand, Single Event Upset at Ground Level, IEEE Transactions on Nuclear Science, vol.43, p.2742, 1996.

. Norm-96b-]-e and . Normand, Single Event Upset in Avionics, IEEE Transactions on Nuclear Science, vol.43, p.461, 1996.

J. Olsen, P. E. Becher, P. B. Fynbo, P. Raaby, and J. Schult, Neutron-Induced Single Event Upsets in Static Rams Observed at 10km Flight Altitude, IEEE Transactions on Nuclear Science, vol.40, pp.120-126, 1993.

. Ch, J. A. Poivey, . E. Barth, K. A. Stassinopoulos, M. Label et al., Implications of Advanced Microelectronics Technologies for Heavy Ion Single Event Effect (SEE) Testing " , Radiation and Its Effects on Components and Systems, th European Conference on, pp.10-14, 2001.

P. Roche, J. M. Palau, K. Belhaddad, G. Bruguier, R. Ecoffet et al., SEU response of an entire SRAM cell simulated as one contiguous three dimensional device domain, IEEE Transactions on Nuclear Science, vol.45, issue.6, pp.2534-2544, 1998.
DOI : 10.1109/23.736495

P. Roche, J. M. Palau, C. Tavernier, G. Bruguier, R. Ecoffet et al., Determination of key parameters for SEU occurrence using 3-D full cell SRAM simulations, IEEE Transactions on Nuclear Science, vol.46, issue.6, pp.1354-1362, 1999.
DOI : 10.1109/23.819093

P. Roche, P. K. Saxena, and N. Bhat, Etude de l'aléa logique (SEU) induit par une particule ionisante dans des mémoires SRAM développées en technologies CMOS avancées Thèse soutenue à l'Université Montpellier 2 le 26 Novembre SEU reliability improvement due to source-side charge collection in the deep-submicron SRAM cell, IEEE Transactions on Device and Materials Reliability, vol.3, issue.1, pp.14-17, 1999.

F. W. Sxton and D. M. , Single event gate rupture in thin gate oxides, IEEE Transactions on Nuclear Science, vol.44, issue.6, pp.2345-2352, 1997.
DOI : 10.1109/23.659060

P. Shivakumar, Modeling the effect of technology trends on the soft error rate of combinational logic, Proceedings International Conference on Dependable Systems and Networks, pp.389-398, 2002.
DOI : 10.1109/DSN.2002.1028924

. P. Shir-01-]-p and . Shirvani, Fault-Tolerant Computing for Radiation Environments, 2001.

E. Taber and . Normand, Single event upset in avionics, IEEE Transactions on Nuclear Science, vol.40, issue.2, pp.120-126, 1993.
DOI : 10.1109/23.212327

K. Tosaka, T. Suzuki, and . Sugii, Alpha particle induced soft errors in submicron SOI SRAM, Symposium on VLSI Technology Digest of Technical Papers, pp.39-40, 1995.

H. Tosaka, T. Kanata, S. Itakura, and . Satoh, Simulation Technologies for Cosmic Ray Neutron-Induced Sof Errors: Models and Simulation Systems, IEEE Transactions on Nuclear Science, vol.46, issue.3, 1999.

R. Velazco, L. Anghel, F. Kaddour, and S. Saleh, A methodology for test replacement solutions of obsolete processors, 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003., 2003.
DOI : 10.1109/OLT.2003.1214400

URL : https://hal.archives-ouvertes.fr/hal-00005832

R. Velazco, E. Kolokithas, and H. Ziade, A microprocessor test approach allowing fault localisation, Proceedings. of the Internaitonal Test Conference, pp.737-743, 1985.
URL : https://hal.archives-ouvertes.fr/hal-00013342

R. L. Woodruff and P. J. Rudeck, Three-dimensional numerical simulation of single event upset of an SRAM cell, IEEE Transactions on Nuclear Science, vol.40, issue.6, pp.1795-1803, 1993.
DOI : 10.1109/23.273477

F. L. Yang and R. A. Saleh, Simulation and analysis of transient faults in digital circuits, IEEE Journal of Solid-State Circuits, vol.27, issue.3, pp.258-264, 1992.
DOI : 10.1109/4.121546

J. F. Ziegler, J. P. Biersack, and U. Littmark, The Stopping and Range of Ions in Matter, 1985.
DOI : 10.1007/978-1-4615-8103-1_3

J. F. Ziegler, H. W. Curtis, and H. P. Muhlfeld, IBM experiments in soft fails in computer electronics, IBM Journal of Research and Development, vol.40, 1978.

J. A. Ziutendyk, Heavy Ion induced SEU in IC's, ESA electronic Conference, pp.12-16, 1990.