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Méthodes de simulation des erreurs transitoires à plusieurs niveaux d'abstraction

Abstract : The nowadays miniaturization of the electronic components increases considerably the sensitivity of the integrated circuits face to transient faults (SEU) or (SET). The analysis of the transient faults sensitivity for combinational logic and sequential circuits is an essential task today. The analytical methods based on probabilistic calculation of the generation of transient pulses SET or SEU, and of the propagation and the transformation of these transients faults into errors, published in the literature are not complete because a certain number of parameters are not taken into account. In this thesis, we propose a fast and accurate multi levels methodology to simulate transient faults. This methodology is a collection of simulation methods, a method for each level of abstraction (physical level, transistor level, and gate level). At the physical level, we use a physical simulation at the components level for any elementary logical gates which consists in the characterization of each type of transistor of a given technology face of SET by taking into account several parameter (the energy or the LET of the particle, the angle of incidence, the impact localization and the dimensions of the transistors where the particle strike occurs). After this characterization, a family of current curves is obtained for each transistor and a domain of the current amplitude values and the current pulses duration is established. The transformation of the current pulse obtained at the physical level into voltage pulses is done by electrical simulations by taking into account the output impedance of each gate. A family of transient voltage pulse curves is also established for each gate. Furthermore, a logical pulse model is defined for these pulses which will be then used in a numerical simulations, which are much faster, and which are finally used in the sensitivity analysis phase for complex circuit. The results of this analysis are used in order to realize a cartography of a complex circuit sensitivity which allow us to determine the most significant zones of a studied circuit and, if required, to decide a hardening solution of the sensitive gates.
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Submitted on : Friday, June 24, 2005 - 11:00:28 AM
Last modification on : Thursday, November 19, 2020 - 3:56:19 PM
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  • HAL Id : tel-00009587, version 1

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S. Saleh. Méthodes de simulation des erreurs transitoires à plusieurs niveaux d'abstraction. Micro et nanotechnologies/Microélectronique. Institut National Polytechnique de Grenoble - INPG, 2005. Français. ⟨tel-00009587⟩

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