Abstract : The probability of transient faults increases with the evolution of technologies. There is a corresponding increased demand for an early analysis of erroneous behaviours. This work concerns the study of two complementary aspects: fault injection in circuits described in RT-level VHDL and analysis of the results obtained at the end of a fault injection campaign.
We present a new approach for mutant generation, allowing circuit instrumentation for heterogeneous fault models. The proposed analysis flow allows a designer to mix single bit-flips (SEU), multiple bit-flips and erroneous transitions when defining a fault injection campaign. Furthermore, we target the most efficient generation with respect to multiple constraints, including (1) simple and automatic modification of the initial circuit description, (2) limited set of additional inputs for injection control and (3) limited hardware overhead after synthesis for compatibility with emulation-based fault injection campaigns.
In the analysis flow, a behavioural model is generated, allowing the designer to identify the detailed error propagation paths in the circuit. Such an analysis aims at identifying very early in the design flow the unacceptable failure modes of a circuit, in order to immediately modify its description to improve its robustness.
We report on results obtained with multi-level fault injections in VHDL descriptions of digital circuits. These results show that an analysis performed at a very early stage in the design process can actually give a helpful insight into the response of a circuit when a fault occurs.