Skip to Main content Skip to Navigation

Conception de réseaux de communication sur puce asynchrones : application aux architectures GALS

Abstract : This thesis tackles a research on self-timed communication architectures for the design of asynchronous Networks-on-Chip (NoCs), dedicated to Globally-Asynchronous Locally-Synchronous (GALS) systems. This study also takes part within the framework of the TIMA Asynchronous Synthesis Tool (TAST) suite.
The needs for communication within modern Systems-on-Chip (SoCs) turns the interconnect network into a major contributor of complexity and performances of these systems. Among many existing methodologies adressing the problem of synchronization within SoCs, this work demonstrates the advantages to choose an asynchronous interconnect network for the communication of GALS systems.
This manuscript puts forward a design methodology for interconnect networks which uses the modularity property of asynchronous circuits. We cut out the construction of our asynchronous NoCs in four major modules: arbitration, transport, routing and synchronization. The aim of this classification is to help the automatic synthesis of arbiters and of asynchronous interconnect networks using TAST. The basic modules of these communication networks are specified in CHP (Communicating Hardware Processes) language. CHP is a high-level modelling language adapted to describe and to synthesize asynchronous circuits. Through these modelling, the proposed methodology throws into relief arbitration and synchronization problems between concurrent elements of the system. Also, a communication system case-study is presented to illustrate the asynchronous NoC design methodology and its current automation level.
Complete list of metadata
Contributor : Lucie Torella <>
Submitted on : Monday, March 21, 2005 - 11:10:52 AM
Last modification on : Friday, December 11, 2020 - 8:28:04 AM
Long-term archiving on: : Friday, April 2, 2010 - 9:44:57 PM


  • HAL Id : tel-00008830, version 1




J. Quartana. Conception de réseaux de communication sur puce asynchrones : application aux architectures GALS. Micro et nanotechnologies/Microélectronique. Institut National Polytechnique de Grenoble - INPG, 2004. Français. ⟨tel-00008830⟩



Record views


Files downloads