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Synthèse logique de circuits asynchrones micropipeline

Abstract : The inherent asynchronous circuit features (modularity, clockless system, local control) brings a serious alternative to face the problems encountered by the silicon integration of more and more complex applications. The main bottleneck to adopt the asynchronous logic is due to the lack of methodologies and efficient tools for this kind of design. The thesis works aim to define a micropipeline asynchronous design methodology. The micropipeline synthesis approach use both commercial tools for data path synthesis and specific tools for asynchronous control synthesis (« STG » using Petrify, « BURST MODE » using Minimalist). The overall methodology for the modelling and the synthesis of asynchronous circuits is based on the DTL specification (Data Transfer Level) which assumes a restriction of source code allowing a rapid and systematic synthesis and targeting several kinds of asynchronous circuits. This design methodology starts from a high level programming language named CHP (Concurrent Hardware Processes) and generates a gate netlist composed of elementary logic and Muller gates. This synthesis methodology has been prototyped. This prototype has been designed for its integration in the TAST automatic asynchronous design flow (Tima Asynchronous Synthesis Tool) which generate QDI circuits, to spread it in the generation of micropipelines circuits. Furthermore, the synthesis methodology has been extended for different kinds of asynchronous controller to improve performances such as speed and energy consumption.
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Contributor : Lucie Torella <>
Submitted on : Tuesday, February 8, 2005 - 12:44:52 PM
Last modification on : Friday, December 11, 2020 - 8:28:04 AM
Long-term archiving on: : Friday, April 2, 2010 - 9:50:04 PM


  • HAL Id : tel-00008398, version 1




A. Rezzag. Synthèse logique de circuits asynchrones micropipeline. Micro et nanotechnologies/Microélectronique. Institut National Polytechnique de Grenoble - INPG, 2004. Français. ⟨tel-00008398⟩



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