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Theses

Validation de Spécifications de Circuits Asynchrones : Méthodes et outils

Abstract : Asynchronous designs aim at answering the increasingly complex problems (clock distribution, energy, modularity) encountered by the synchronous circuits designers. Asynchronous circuits, contrary to the synchronous circuits, are not ordered by a global clock. Even medium size asynchronous circuits may display a complex behavior, due to the combinational explosion in the chronology of events that may happen. It is thus essential to apply rigorous design and validation methods.This thesis work addresses the analysis and the automatic validation of asynchronous specifications written in the CHP, prior to their synthesis with the TAST asynchronous design flow developed by the CIS group of TIMA.Two approaches are proposed. In the first approach we use symbolic model checking and pseudo-synchronous modeling, to perform property checking on RTL designs. The approach consisted in translating the Petri Net, interpreted as a finite state machine, as a pseudo-synchronous VHDL description, which can then be input to industrial symbolic modelchecking software. In the second approach, CHP semantics, initially given in terms of Petri Nets, are reformulated as Extended Labeled Transition Systems (ELTS). Circuit specifications are then validated using enumerative model checking tools. To increase the performances of the enumerative approach and
avoid the state explosion problem, we have developed and implemented several automatic reduction and abstraction techniques.
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Submitted on : Thursday, December 16, 2004 - 11:31:10 AM
Last modification on : Friday, December 11, 2020 - 8:28:04 AM
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  • HAL Id : tel-00007774, version 1

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M. Boubekeur. Validation de Spécifications de Circuits Asynchrones : Méthodes et outils. Autre [cs.OH]. Université Joseph-Fourier - Grenoble I, 2004. Français. ⟨tel-00007774⟩

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